From: Wolfram Sang <wsa@sang-engineering.com>
To: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Cc: linux-i2c@vger.kernel.org
Subject: Re: i2c-slave-testunit over i2c-gpio bus
Date: Tue, 18 Feb 2025 11:02:37 +0100 [thread overview]
Message-ID: <Z7RavX4Ro26AZJir@ninjato> (raw)
In-Reply-To: <CAJs94EaBRDkx5grA2yC=e_Zgut4RK0ZGQnUS2Vc0fABTC9UJSw@mail.gmail.com>
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> Thanks. But isn't it possible to attach an interrupt handler to SCL
> GPIO? Or do you mean that the latency for IRQ handling is too high?
Way too high for most systems. I made the in-kernel sloppy GPIO logic
analyzer. From that experience, even with constant polling using an
isolated CPU core, you would need at least a dedicatded 300MHz core to
monitor 100kHz. With interrupts, it will probably be a magnitutde more.
I scrapped that idea for the above analyzer, too slow.
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next prev parent reply other threads:[~2025-02-18 10:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 8:49 i2c-slave-testunit over i2c-gpio bus Matwey V. Kornilov
2025-02-18 9:44 ` Wolfram Sang
2025-02-18 9:46 ` Matwey V. Kornilov
2025-02-18 10:02 ` Wolfram Sang [this message]
2025-02-18 10:21 ` Matwey V. Kornilov
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