Re: [PATCH] dt-bindings: xilinx: Switch xilinx.com emails to amd.com

Michal Simek
2023-06-05T11:11:18Z

út 16. 5. 2023 v 15:51 odesílatel Michal Simek <michal.simek@amd.com> napsal:
>
> @xilinx.com is still working but better to switch to new amd.com after
> AMD/Xilinx acquisition.
>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> Documentation/devicetree/bindings/arm/xilinx.yaml | 2 +-
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 2 +-
> .../devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 2 +-
> Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +-
> Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml | 4 ++--
> .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 2 +-
> .../devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml | 2 +-
> Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml | 2 +-
> .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml | 2 +-
> Documentation/devicetree/bindings/gpio/gpio-zynq.yaml | 2 +-
> Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml | 2 +-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 2 +-
> Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 2 +-
> .../devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 2 +-
> .../devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml | 2 +-
> .../bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 2 +-
> .../bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 2 +-
> Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 2 +-
> .../devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 2 +-
> .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 2 +-
> .../devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml | 2 +-
> Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml | 2 +-
> Documentation/devicetree/bindings/serial/cdns,uart.yaml | 2 +-
> Documentation/devicetree/bindings/spi/spi-cadence.yaml | 2 +-
> Documentation/devicetree/bindings/spi/spi-xilinx.yaml | 2 +-
> Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml | 2 +-
> Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml | 2 +-
> Documentation/devicetree/bindings/timer/cdns,ttc.yaml | 2 +-
> .../devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml | 4 ++--
> 29 files changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml
> index b3071d10ea65..f57ed0347894 100644
> --- a/Documentation/devicetree/bindings/arm/xilinx.yaml
> +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq Platforms
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> description: |
> Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index 71364c6081ff..b29ce598f9aa 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Ceva AHCI SATA Controller
>
> maintainers:
> - - Piyush Mehta <piyush.mehta@xilinx.com>
> + - Piyush Mehta <piyush.mehta@amd.com>
>
> description: |
> The Ceva SATA controller mostly conforms to the AHCI interface with some
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> index c1f04830a832..02bd556bd91a 100644
> --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx clocking wizard
>
> maintainers:
> - - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
>
> description:
> The clocking wizard is a soft ip clocking block of Xilinx versal. It
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> index 229af98b1d30..93ae349cf9e9 100644
> --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Versal clock controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
> - Jolly Shah <jolly.shah@xilinx.com>
> - Rajan Vaja <rajan.vaja@xilinx.com>
>
> diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
> index 9e8fbd02b150..8aead97a585b 100644
> --- a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
> +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
> @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx ZynqMP AES-GCM Hardware Accelerator
>
> maintainers:
> - - Kalyani Akula <kalyani.akula@xilinx.com>
> - - Michal Simek <michal.simek@xilinx.com>
> + - Kalyani Akula <kalyani.akula@amd.com>
> + - Michal Simek <michal.simek@amd.com>
>
> description: |
> The ZynqMP AES-GCM hardened cryptographic accelerator is used to
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> index f14f7b454f07..910bebe6cfa8 100644
> --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx firmware driver
>
> maintainers:
> - - Nava kishore Manne <nava.manne@xilinx.com>
> + - Nava kishore Manne <nava.kishore.manne@amd.com>
>
> description: The zynqmp-firmware node describes the interface to platform
> firmware. ZynqMP has an interface to communicate with secure firmware.
> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
> index f47b6140a742..04dcadc2c20e 100644
> --- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
> +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq FPGA Manager
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> index ac6a207278d5..26f18834caa3 100644
> --- a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Versal FPGA driver.
>
> maintainers:
> - - Nava kishore Manne <nava.manne@xilinx.com>
> + - Nava kishore Manne <nava.kishore.manne@amd.com>
>
> description: |
> Device Tree Versal FPGA bindings for the Versal SoC, controlled
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
> index 00a8d92ff736..1390ae103b0b 100644
> --- a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
>
> maintainers:
> - - Nava kishore Manne <navam@xilinx.com>
> + - Nava kishore Manne <nava.kishore.manne@amd.com>
>
> description: |
> Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> index 572e1718f501..5e2496379a3c 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq GPIO controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
> index f333ee2288e7..c1060e5fcef3 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx AXI GPIO controller
>
> maintainers:
> - - Neeli Srinivas <srinivas.neeli@xilinx.com>
> + - Neeli Srinivas <srinivas.neeli@amd.com>
>
> description:
> The AXI GPIO design provides a general purpose input/output interface
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> index 31c0fc345903..18e61aff2185 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> @@ -12,7 +12,7 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <piyush.mehta@xilinx.com>
> + - Piyush Mehta <piyush.mehta@amd.com>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
> index cb24d7b3221c..ff57c5416ebc 100644
> --- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
> +++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Cadence I2C controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> allOf:
> - $ref: /schemas/i2c/i2c-controller.yaml#
> diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
> index 374ffe64016f..aeaddbf574b0 100644
> --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
> @@ -33,7 +33,7 @@ description: |
> +------------------------------------------+
>
> maintainers:
> - - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> index 7d77823dbb7a..43daf837fc9f 100644
> --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx MIPI CSI-2 Receiver Subsystem
>
> maintainers:
> - - Vishal Sagar <vishal.sagar@xilinx.com>
> + - Vishal Sagar <vishal.sagar@amd.com>
>
> description: |
> The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
> diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> index e68c4306025a..6b62d5d83476 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> @@ -9,7 +9,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
> maintainers:
> - Krzysztof Kozlowski <krzk@kernel.org>
> - Manish Narani <manish.narani@xilinx.com>
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> description: |
> Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
> diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
> index 8f72e2f8588a..7864a1c994eb 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
> @@ -9,7 +9,7 @@ title: Zynq A05 DDR Memory Controller
> maintainers:
> - Krzysztof Kozlowski <krzk@kernel.org>
> - Manish Narani <manish.narani@xilinx.com>
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> description:
> The Zynq DDR ECC controller has an optional ECC support in half-bus width
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index 24ddc2855b94..4734be456bde 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: CPM Host Controller device tree for Xilinx Versal SoCs
>
> maintainers:
> - - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> + - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
>
> allOf:
> - $ref: /schemas/pci/pci-bus.yaml#
> diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
> index 598a042850b8..b85f9e36ce4b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq Pinctrl
>
> maintainers:
> - - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
>
> description: |
> Please refer to pinctrl-bindings.txt in this directory for details of the
> diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
> index 2722dc7bb03d..cdebfa991e06 100644
> --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx ZynqMP Pinctrl
>
> maintainers:
> - - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
> - Rajan Vaja <rajan.vaja@xilinx.com>
>
> description: |
> diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
> index 11f1f98c1cdc..45792e216981 100644
> --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
> +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq MPSoC Power Management
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> description: |
> The zynqmp-power node describes the power management configurations.
> diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> index 7ed0230f6c67..d1f5eb996dba 100644
> --- a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> @@ -11,7 +11,7 @@ description:
> The RTC controller has separate IRQ lines for seconds and alarm.
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> allOf:
> - $ref: rtc.yaml#
> diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> index a8b323d7bf94..e35ad1109efc 100644
> --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Cadence UART Controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> index b0f83b5c2cdd..b7552739b554 100644
> --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Cadence SPI controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> allOf:
> - $ref: spi-controller.yaml#
> diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml
> index 6bd83836eded..4beb3af0416d 100644
> --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx SPI controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> allOf:
> - $ref: spi-controller.yaml#
> diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
> index 226d8b493b57..e5199b109dad 100644
> --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> allOf:
> - $ref: spi-controller.yaml#
> diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
> index 83e8fb4a548d..7ea8fb42ce2c 100644
> --- a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
> @@ -14,7 +14,7 @@ allOf:
> - $ref: spi-controller.yaml#
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> # Everything else is described in the common file
> properties:
> diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml
> index bc5e6f226295..dbba780c9b02 100644
> --- a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml
> +++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml
> @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Cadence TTC - Triple Timer Counter
>
> maintainers:
> - - Michal Simek <michal.simek@xilinx.com>
> + - Michal Simek <michal.simek@amd.com>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
> index 8444c56dd602..dc1ff39d05a0 100644
> --- a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
> @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx AXI/PLB softcore and window Watchdog Timer
>
> maintainers:
> - - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> - - Srinivas Neeli <srinivas.neeli@xilinx.com>
> + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> + - Srinivas Neeli <srinivas.neeli@amd.com>
>
> description:
> The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
> --
> 2.36.1
>

Applied.
M

--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs