From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Yann Sionneau <ysionneau@kalrayinc.com>
Cc: Jan Bottorff <janb@os.amperecomputing.com>,
Jarkko Nikula <jarkko.nikula@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Jan Dabros <jsd@semihalf.com>, Andi Shyti <andi.shyti@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] i2c: designware: Fix corrupted memory seen in the ISR
Date: Wed, 13 Sep 2023 14:22:17 +0300 [thread overview]
Message-ID: <ZQGbaXTnIk0NIZbK@smile.fi.intel.com> (raw)
In-Reply-To: <4537fa1c-b622-674c-026e-8453eda0a4d1@kalrayinc.com>
On Wed, Sep 13, 2023 at 11:04:00AM +0200, Yann Sionneau wrote:
> On 13/09/2023 03:03, Jan Bottorff wrote:
...
> > + /*
> > + * To guarantee data written by the current core is visible to
> > + * all cores, a write barrier is required. This needs to be
> > + * before an interrupt causes execution on another core.
> > + * For ARM processors, this needs to be a DSB barrier.
> > + */
> > + wmb();
>
> Apart from the commit message it looks good to me.
>
> If I understand correctly without this wmb() it is possible that the writes
> to dev->msg_write_idx , dev->msg_read_idx = 0 etc would not yet be visible
> to another CPU running the ISR handler right after enabling those.
If this is the case, shouldn't we rather use READ_ONCE()/WRITE_ONCE() where
appropriate?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2023-09-13 11:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-13 1:03 [PATCH] i2c: designware: Fix corrupted memory seen in the ISR Jan Bottorff
2023-09-13 9:04 ` Yann Sionneau
2023-09-13 11:22 ` Andy Shevchenko [this message]
2023-09-13 11:32 ` Yann Sionneau
2023-09-13 11:54 ` Yann Sionneau
2023-09-13 20:16 ` Jan Bottorff
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