From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B035B219A80; Sat, 12 Apr 2025 19:45:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744487103; cv=none; b=Bdqu65YO9qmV8uUKEn8uVSd/JZaftZLwHOiceDM26lGelipnN90P3nRCr6WB6uHzVF0yEMrMS5KS+aE/3y29uy118WTWdmdNgiumNtw+zxBEId1qsQG0vcObslBvViMLqau0QxgwiApmE6jEDJqme1VZoD4EmiFCVPgzL0rXNJc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744487103; c=relaxed/simple; bh=kzSNmSKS9hY5c47HY+wXva7VoPSYzrY/19XJ4KoEFKQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CGdOPyaUDfN/UbIUwoNWIoyiD3ovmi/e11Ax/HT5RRNBB64Xf973UkV1YLbTy/gMkEogtC2iUGy5KniuIVY2cg/MpuLp/kMoza8D00gi4DF2WmLdHNWq2tq74rxpk2QlXgC9eZyXSZ/8YMzw/3cvOfafq0N/zy4mmgW7fYx6X/E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lzuHVdrl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lzuHVdrl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30A27C4CEE3; Sat, 12 Apr 2025 19:44:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744487103; bh=kzSNmSKS9hY5c47HY+wXva7VoPSYzrY/19XJ4KoEFKQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lzuHVdrls0xTg+r1JSH990eoUnF3q16yRYwgF92HWtKRFIxN+JgbmbbZLpaEG+CR+ hKXS/UXg0N0n+/xET/GvjuRfRJGCtBtqF96kSIXmgL9NnzPMWAHyC7x6txUoCmW3rd xngJDT/1hwBgzlDZAvHE+fy0x+rcimEsJQfm1OI45rw33uectul4cGEpQArE5zwjiz c9ATmj7VGZIeFWSyRSqlPFB4C4qTzj3be2Lh957o9jCjPrH3fVGEqWSiaAvPMzsSr0 6+hgyydHtGemhDu6yVkDSbaJmQ9jIaFCdPjByigwodCfQU3GUpfHJiXk2TXYJWpCXB JiA9V2L/DMYWQ== Date: Sat, 12 Apr 2025 21:44:56 +0200 From: Ingo Molnar To: Borislav Petkov Cc: Mario Limonciello , Jean Delvare , Andi Shyti , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Jonathan Corbet , Mario Limonciello , Yazen Ghannam , Thomas Gleixner , Ingo Molnar , Dave Hansen , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , Shyam Sundar S K , Hans de Goede , "open list:DOCUMENTATION" , open list , "open list:I2C/SMBUS CONTROLLER DRIVERS FOR PC" , "open list:AMD PMC DRIVER" Subject: Re: [PATCH v3 2/4] i2c: piix4: Move SB800_PIIX4_FCH_PM_ADDR definition to amd_node.h Message-ID: References: <20250410200202.2974062-1-superm1@kernel.org> <20250410200202.2974062-3-superm1@kernel.org> <20250411114908.GLZ_kBtN94h79EEN6j@fat_crate.local> <20250411124157.GDZ_kOFfsGgY4zUXA5@fat_crate.local> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250411124157.GDZ_kOFfsGgY4zUXA5@fat_crate.local> * Borislav Petkov wrote: > On Fri, Apr 11, 2025 at 07:09:56AM -0500, Mario Limonciello wrote: > > I was aiming for a header that we would conceivably use in all these places > > anyway. > > > > Can you suggest a more fitting existing header? A new one felt too heavy > > for a single register define. > > No, the logic is: put it in the *right* header. Not in the "whatever-works" > header. Yeah, it's the Linux kernel equivalent of: 'if you touch it, you own it', a.k.a. 'no good deed goes unpunished'. ;-) > So you can easily add a > > arch/x86/include/asm/platform.h > > header which contains exactly platform stuff. And FCH sounds like a platform > thing to me. Or at least southbridge or whatever that thing is called now. It > certainly ain't part of the CPU so platform should be more fitting. > > Unless someone has a better idea... Yeah, so I think we can create a brand new header or so, because it's an AMD SB800 southbridge chipset register? We already have . 'platform' might be a bit too generic and fungible I think: often the northbridge and the CPU is considered part of a 'platform' too. Thanks, Ingo