Re: i2c: designware: unhandled interrupt on N100 lpss channel 0

Andy Shevchenko
2024-03-20T21:07:58Z

On Wed, Mar 20, 2024 at 09:21:34PM +0100, Heiner Kallweit wrote:
> On 20.03.2024 16:59, Andy Shevchenko wrote:
> > On Wed, Mar 20, 2024 at 03:56:29PM +0100, Heiner Kallweit wrote:

...

> > grep 0000001b /sys/kernel/debug/pinctrl/*/pins
>
> pin 3 (GPPC_B_3) 3:INTC1057:00 GPIO 0x80100102 0x0000001b 0x00000000 [LOCKED tx]
> pin 82 (GPP_F_7_EMMC_CMD) 135:INTC1057:00 GPIO 0x44000300 0x0000001b 0x00000000 [LOCKED full, ACPI]
> pin 182 (GPPC_C_13) 269:INTC1057:00 GPIO 0x44000300 0x0000001b 0x00000000 [LOCKED full, ACPI]

I was not correct, the value to grep is '0000[0-3][0-9a-f]1b' as there pull
up/down can be enabled.

Nevertheless from the above the pin 3 is one that is enabled as GPIO input with
RTE 27 and direct IRQ. If it's a culprit, try to add in the pinctrl-intel.c at
the end of .probe:

{
void __iomem *padcfg0;
u32 value;

padcfg0 = intel_get_padcfg(pctrl, 3, PADCFG0);

value = readl(padcfg0);
value |= PADCFG0_GPIOTXDIS;
value |= PADCFG0_GPIORXDIS;
writel(value, padcfg0);
}

If it helps, it will show the BIOS bug (likely).

--
With Best Regards,
Andy Shevchenko