Re: i2c: designware: unhandled interrupt on N100 lpss channel 0

Andy Shevchenko
2024-03-20T14:15:39Z

On Wed, Mar 20, 2024 at 03:37:34PM +0200, Jarkko Nikula wrote:
> On 3/20/24 2:27 PM, Heiner Kallweit wrote:
> > On 19.03.2024 22:11, Heiner Kallweit wrote:
> > > On a N100-based mini pc I see the following. I found older reports with the same symptom,
> > > but root cause seems to be different.
> > >
> > > - Interrupt 27 is not shared in my case
> > > - I checked register values on entering the ISR. Interrupt mask and DW_IC_RAW_INTR_STAT
> > > are both 0.
> > > - After an interrupt storm of 100,000 interrupts the interrupt gets disabled
> > > - The issue affects channel 0 only
> > >
> > > If not the I2C IP, then who else can touch the interrupt line?
> >
> > I noticed that after including INTEL_IDMA64 in my config the problem no longer occurs.
> > So there seems to be a dependency. Should it be reflected in Kconfig, e.g.
> > make MFD_INTEL_LPSS dependent on INTEL_IDMA64, or let it imply INTEL_IDMA64?
> >
> Hmm.. interesting. I'd say BIOS perhaps has left the IDMA active and is
> generating interrupts until the idma64 driver acknowledges it.
>
> There should not be generic dependency since the i2c_designware is not using
> the DMA and a quick test on one platform where idma64 and i2c_designware are
> sharing the same interrupt without CONFIG_INTEL_IDMA64 not set didn't show
> similar behavior.
>
> Andy: Do you have any additional ideas or debug hints to this?

Can you share `cat /proc/interrupts` in non-working and working cases?

Just to confirm: loading idma64 driver fixes the issue, correct?

--
With Best Regards,
Andy Shevchenko