Re: [PATCH v1 3/3] i2c: imx: prevent rescheduling in non dma mode

[Stefan Eichenberger <eichest@gmail.com>]

Hi Frank,

On Mon, Jul 15, 2024 at 01:03:26PM -0400, Frank Li wrote:
> > +static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx)
> > +{
> > +	unsigned int temp;
> > +
> > +	if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) {
> > +		if (i2c_imx->is_lastmsg) {
> > +			/*
> > +			 * It must generate STOP before read I2DR to prevent
> > +			 * controller from generating another clock cycle
> > +			 */
> > +			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
> > +			if (!(temp & I2CR_MSTA))
> > +				i2c_imx->stopped =  1;
> > +			temp &= ~(I2CR_MSTA | I2CR_MTX);
> > +			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +		} else {
> > +			/*
> > +			 * For i2c master receiver repeat restart operation like:
> > +			 * read -> repeat MSTA -> read/write
> > +			 * The controller must set MTX before read the last byte in
> > +			 * the first read operation, otherwise the first read cost
> > +			 * one extra clock cycle.
> > +			 */
> > +			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
> > +			temp |= I2CR_MTX;
> > +			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +		}
> > +	} else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) {
> > +		temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
> > +		temp |= I2CR_TXAK;
> > +		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +	}
> > +
> > +	i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
> 
> Why not use loop to read all data from FIFO? I think read_reg use readb(),
> suggest change to readb_relaxed(). The similar case for writeb. dma_engine
> will use writel() at least once when start DMA. it should be enough for
> memory barrier. 
> 
> Because it move to irq handle, writex__relaxed() will help reduce some
> register access time.
> 

I think there is not FIFO on the i.MX I2C controller, or do I miss
something? In the i.MX 8M Plus reference manual they write for example:
> In Master Receive mode, reading the data register allows a read to occur
> and initiates the next byte to be received.

I will test the changes with readb_relaxed() and writeb_relaxed() and
see what happens, thanks a lot for the hint.

Regards,
Stefan