From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Rengarajan S <rengarajan.s@microchip.com>
Cc: tharunkumar.pasumarthi@microchip.com,
kumaravel.thiagarajan@microchip.com,
UNGLinuxDriver@microchip.com, andi.shyti@kernel.org,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset disable support for Rev C0+ devices
Date: Thu, 25 Sep 2025 22:34:00 +0200 [thread overview]
Message-ID: <aNWnOOg5KY_8K1DO@shikoro> (raw)
In-Reply-To: <20250925140049.14454-1-rengarajan.s@microchip.com>
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On Thu, Sep 25, 2025 at 07:30:48PM +0530, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its SMBUS
> controller registers reset to hardware default values. This results
> in device inaccessibility and I2C read/write failure. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the SMBUS registers during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
>
> Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
Tharun? Kumaravel? Do you have time to look at these patches?
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next prev parent reply other threads:[~2025-09-25 20:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 14:00 [PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset disable support for Rev C0+ devices Rengarajan S
2025-09-25 14:00 ` [PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: Update minimum bus idle time Rengarajan S
2025-09-25 20:34 ` Wolfram Sang [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-08-26 3:40 [PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset disable support for Rev C0+ devices Rengarajan S
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