[PATCH V3 2/2] i2c: imx: add abort path for invalid block length

LI Qingwu
2026-01-16T11:19:15Z

When a block read returns an invalid length (0 or >I2C_SMBUS_BLOCK_MAX),
the current implementation leaves the bus hanging with SDA held low,
blocking all further I2C communication on the bus.

Add a dedicated IMX_I2C_STATE_READ_BLOCK_DATA_ABORT state and ISR
handler to properly terminate the transfer when an invalid block length
is detected:
- Set TXAK and receive the next byte with NACK
- On the following interrupt, generate a Stop condition
- Read and discard the final byte
- Report -EPROTO to the caller

This ensures the bus is released correctly and allows other devices on
the bus to continue operating normally.

Tested on i.MX 8M Plus with continuous block read operations.

Signed-off-by: LI Qingwu <Qing-wu.Li@leica-geosystems.com.cn>
---
drivers/i2c/busses/i2c-imx.c | 55 ++++++++++++++++++++++++++++++++++--
1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 05ba41144648..d3fbc2df7f04 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -232,6 +232,7 @@ enum imx_i2c_state {
IMX_I2C_STATE_READ_CONTINUE,
IMX_I2C_STATE_READ_BLOCK_DATA,
IMX_I2C_STATE_READ_BLOCK_DATA_LEN,
+ IMX_I2C_STATE_READ_BLOCK_DATA_ABORT,
};

struct imx_i2c_struct {
@@ -1053,14 +1054,60 @@ static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx)
i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
}

+static inline void i2c_imx_isr_read_block_data_abort(struct imx_i2c_struct *i2c_imx)
+{
+ unsigned int temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
+
+ if (i2c_imx->is_lastmsg) {
+ /*
+ * Last byte to read.
+ *
+ * Ref: IMX8MPRM Rev. 1, 06/2021: 17.1.4.4 Generation of Stop
+ *
+ * Ref: IMX8MPRM Rev. 1, 06/2021: Figure 17-5.
+ * Flowchart of typical I2C interrupt routine
+ *
+ * Before the last byte is read, a Stop signal must be generated.
+ */
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
+ if (!(temp & I2CR_MSTA))
+ i2c_imx->stopped = 1;
+ temp &= ~(I2CR_MSTA | I2CR_MTX);
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
+ imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
+ i2c_imx->state = IMX_I2C_STATE_FAILED;
+ wake_up(&i2c_imx->queue);
+ } else {
+ /*
+ * Next-to-last byte to read.
+ *
+ * Ref: IMX8MPRM Rev. 1, 06/2021: 17.1.4.4 Generation of Stop
+ *
+ * Ref: IMX8MPRM Rev. 1, 06/2021: Figure 17-5.
+ * Flowchart of typical I2C interrupt routine
+ *
+ * For a master receiver to terminate a data transfer, it must
+ * inform the slave transmitter by not acknowledging the last
+ * data byte. This is done by setting the transmit acknowledge
+ * bit (I2C_I2CR[TXAK]) before reading the next-to-last byte.
+ */
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
+ temp |= I2CR_TXAK;
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
+ imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
+ i2c_imx->is_lastmsg = true;
+ }
+}
+
static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx)
{
u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);

if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) {
i2c_imx->isr_result = -EPROTO;
- i2c_imx->state = IMX_I2C_STATE_FAILED;
- wake_up(&i2c_imx->queue);
+ i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_ABORT;
+ i2c_imx->is_lastmsg = false;
+ return;
}
i2c_imx->msg->len += len;
i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = len;
@@ -1106,6 +1153,10 @@ static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned i
i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE;
break;

+ case IMX_I2C_STATE_READ_BLOCK_DATA_ABORT:
+ i2c_imx_isr_read_block_data_abort(i2c_imx);
+ break;
+
case IMX_I2C_STATE_WRITE:
if (i2c_imx_isr_write(i2c_imx))
break;
--
2.43.0