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Date: Thu, 22 Jan 2026 18:32:35 +0100
From: Andi Shyti <andi.shyti@kernel.org>
To: Kartik Rajput <kkartik@nvidia.com>
Cc: ldewangan@nvidia.com, digetx@gmail.com, thierry.reding@gmail.com, 
	jonathanh@nvidia.com, akhilrajeev@nvidia.com, smangipudi@nvidia.com, 
	linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 2/4] i2c: tegra: Move variant to tegra_i2c_hw_feature
Message-ID: <aXJe_2JC7KgfBgLa@zenone.zhora.eu>
References: <20260121153012.92243-1-kkartik@nvidia.com>
 <20260121153012.92243-3-kkartik@nvidia.com>
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In-Reply-To: <20260121153012.92243-3-kkartik@nvidia.com>

Hi Kartik,

> @@ -280,7 +282,6 @@ struct tegra_i2c_hw_feature {
>   * @base_phys: physical base address of the I2C controller
>   * @cont_id: I2C controller ID, used for packet header
>   * @irq: IRQ number of transfer complete interrupt
> - * @variant: This represents the I2C controller variant.
>   * @msg_complete: transfer completion notifier
>   * @msg_buf_remaining: size of unsent data in the message buffer
>   * @msg_len: length of message in current transfer
> @@ -332,13 +333,12 @@ struct tegra_i2c_dev {
>  	bool atomic_mode;
>  	bool dma_mode;
>  	bool msg_read;
> -	enum tegra_i2c_variant variant;
>  };
>  
>  #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \
> -		     (dev)->variant == TEGRA_I2C_VARIANT_DVC)
> +		     (dev)->hw->variant == TEGRA_I2C_VARIANT_DVC)
>  #define IS_VI(dev)  (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \
> -		     (dev)->variant == TEGRA_I2C_VARIANT_VI)
> +		     (dev)->hw->variant == TEGRA_I2C_VARIANT_VI)
>  
>  static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
>  		       unsigned int reg)
> @@ -1647,8 +1647,42 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
>  	.has_interface_timing_reg = false,
>  	.enable_hs_mode_support = false,
>  	.has_mutex = false,
> +	.variant = TEGRA_I2C_VARIANT_DEFAULT,
>  };

in v8 I made a question at this point, could you please answer?

Thanks,
Andi