[PATCH v6 20/27] misc: lan966x_pci: Fix dtso nodes ordering

Herve Codina
2026-03-25T14:42:12Z

Nodes available in the dtso are not ordered by their unit address.

Fix that re-ordering them according to their unit address.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/misc/lan966x_pci.dtso | 99 +++++++++++++++++------------------
1 file changed, 49 insertions(+), 50 deletions(-)

diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso
index 7b196b0a0eb6..94a967b384f3 100644
--- a/drivers/misc/lan966x_pci.dtso
+++ b/drivers/misc/lan966x_pci.dtso
@@ -59,6 +59,50 @@ pci-ep-bus@0 {
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;

+ switch: switch@e0000000 {
+ compatible = "microchip,lan966x-switch";
+ reg = <0xe0000000 0x0100000>,
+ <0xe2000000 0x0800000>;
+ reg-names = "cpu", "gcb";
+
+ interrupt-parent = <&oic>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "xtr", "ana";
+
+ resets = <&reset 0>;
+ reset-names = "switch";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tod_pins>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ phy-handle = <&lan966x_phy0>;
+
+ reg = <0>;
+ phy-mode = "gmii";
+ phys = <&serdes 0 CU(0)>;
+ };
+
+ port1: port@1 {
+ phy-handle = <&lan966x_phy1>;
+
+ reg = <1>;
+ phy-mode = "gmii";
+ phys = <&serdes 1 CU(1)>;
+ };
+ };
+ };
+
+ cpu_ctrl: syscon@e00c0000 {
+ compatible = "microchip,lan966x-cpu-syscon", "syscon";
+ reg = <0xe00c0000 0xa8>;
+ };
+
oic: oic@e00c0120 {
compatible = "microchip,lan966x-oic";
#interrupt-cells = <2>;
@@ -67,11 +111,6 @@ oic: oic@e00c0120 {
reg = <0xe00c0120 0x190>;
};

- cpu_ctrl: syscon@e00c0000 {
- compatible = "microchip,lan966x-cpu-syscon", "syscon";
- reg = <0xe00c0000 0xa8>;
- };
-
reset: reset@e200400c {
compatible = "microchip,lan966x-switch-reset";
reg = <0xe200400c 0x4>, <0xe00c0000 0xa8>;
@@ -104,14 +143,6 @@ fc0_a_pins: fcb4-i2c-pins {
pins = "GPIO_9", "GPIO_10";
function = "fc0_a";
};
-
- };
-
- serdes: serdes@e202c000 {
- compatible = "microchip,lan966x-serdes";
- reg = <0xe202c000 0x9c>,
- <0xe2004010 0x4>;
- #phy-cells = <2>;
};

mdio1: mdio@e200413c {
@@ -133,43 +164,11 @@ lan966x_phy1: ethernet-lan966x_phy@2 {
};
};

- switch: switch@e0000000 {
- compatible = "microchip,lan966x-switch";
- reg = <0xe0000000 0x0100000>,
- <0xe2000000 0x0800000>;
- reg-names = "cpu", "gcb";
-
- interrupt-parent = <&oic>;
- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
- <9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "xtr", "ana";
-
- resets = <&reset 0>;
- reset-names = "switch";
-
- pinctrl-names = "default";
- pinctrl-0 = <&tod_pins>;
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port0: port@0 {
- phy-handle = <&lan966x_phy0>;
-
- reg = <0>;
- phy-mode = "gmii";
- phys = <&serdes 0 CU(0)>;
- };
-
- port1: port@1 {
- phy-handle = <&lan966x_phy1>;
-
- reg = <1>;
- phy-mode = "gmii";
- phys = <&serdes 1 CU(1)>;
- };
- };
+ serdes: serdes@e202c000 {
+ compatible = "microchip,lan966x-serdes";
+ reg = <0xe202c000 0x9c>,
+ <0xe2004010 0x4>;
+ #phy-cells = <2>;
};
};
};
--
2.53.0