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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5356a28c01csm356135e87.271.2024.09.05.07.19.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Sep 2024 07:19:11 -0700 (PDT) Message-ID: Date: Thu, 5 Sep 2024 17:18:50 +0300 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/7] i2c: qcom-cci: Stop complaining about DT set clock rate Content-Language: en-US To: Konrad Dybcio , Richard Acayan , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-media@vger.kernel.org References: <20240904020448.52035-9-mailingradian@gmail.com> <20240904020448.52035-12-mailingradian@gmail.com> <917917cc-3e78-4ab6-8fa4-82d9a6fe3fdd@kernel.org> From: Vladimir Zapolskiy In-Reply-To: <917917cc-3e78-4ab6-8fa4-82d9a6fe3fdd@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Konrad, On 9/5/24 16:57, Konrad Dybcio wrote: > On 4.09.2024 4:04 AM, Richard Acayan wrote: >> From: Bryan O'Donoghue >> >> It is common practice in the downstream and upstream CCI dt to set CCI >> clock rates to 19.2 MHz. It appears to be fairly common for initial code to >> set the CCI clock rate to 37.5 MHz. >> >> Applying the widely used CCI clock rates from downstream ought not to cause >> warning messages in the upstream kernel where our general policy is to >> usually copy downstream hardware clock rates across the range of Qualcomm >> drivers. >> >> Drop the warning it is pervasive across CAMSS users but doesn't add any >> information or warrant any changes to the DT to align the DT clock rate to >> the bootloader clock rate. >> >> Signed-off-by: Bryan O'Donoghue >> Reviewed-by: Vladimir Zapolskiy >> Link: https://lore.kernel.org/linux-arm-msm/20240824115900.40702-1-bryan.odonoghue@linaro.org >> Signed-off-by: Richard Acayan >> --- > > I.. am not sure this is really a problem? On some platforms the core > clock is only 19.2 Mhz, but e.g. on sdm845 we have: > > static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { > F(19200000, P_BI_TCXO, 1, 0, 0), > F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), > F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), > F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), > { } > }; > > Shouldn't this be somehow dynamically calculated? > I believe the problem fixed by the change is an unnecessary dev_warn(), in addition it's unclear why the CCI clock rate shall be strictly 37500000 for all "CCI v2" platforms. If the latter is a necessity, then it would be better to set the rate explicitly, however since it's not done for any such platforms, I would say that it is not needed. And if it is not needed, or a default and universal 19.2MHz rate is good enough, then I would suggest to remove everything 'cci_clk_rate' related from the driver, and this makes the change incomplete... -- Best wishes, Vladimir