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[91.76.4.184]) by smtp.googlemail.com with ESMTPSA id a20sm1415679lfl.20.2020.07.16.14.18.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jul 2020 14:18:41 -0700 (PDT) Subject: Re: [RFC PATCH v3 16/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, frankc@nvidia.com, hverkuil@xs4all.nl, sakari.ailus@iki.fi, robh+dt@kernel.org, helen.koike@collabora.com Cc: sboyd@kernel.org, gregkh@linuxfoundation.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <1594786855-26506-1-git-send-email-skomatineni@nvidia.com> <1594786855-26506-17-git-send-email-skomatineni@nvidia.com> <20d63eca-4b2b-584e-a391-a4fb64a16b40@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Fri, 17 Jul 2020 00:18:39 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20d63eca-4b2b-584e-a391-a4fb64a16b40@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org 17.07.2020 00:09, Sowjanya Komatineni пишет: > > On 7/16/20 1:38 PM, Dmitry Osipenko wrote: >> 15.07.2020 07:20, Sowjanya Komatineni пишет: >>> SW can trigger MIPI pads calibration any time after power on >>> but calibration results will be latched and applied to the pads >>> by MIPI CAL unit only when the link is in LP-11 state and then >>> status register will be updated. >>> >>> For CSI, trigger of pads calibration happen during CSI stream >>> enable where CSI receiver is kept ready prior to sensor or CSI >>> transmitter stream start. >>> >>> So, pads may not be in LP-11 at this time and waiting for the >>> calibration to be done immediate after calibration start will >>> result in timeout. >>> >>> This patch splits tegra_mipi_calibrate() and tegra_mipi_wait() >>> so triggering for calibration and waiting for it to complete can >>> happen at different stages. >>> >>> Signed-off-by: Sowjanya Komatineni >>> --- >> ... >>>   int tegra_mipi_calibrate(struct tegra_mipi_device *device) >>>   { >>> @@ -370,12 +381,10 @@ int tegra_mipi_calibrate(struct >>> tegra_mipi_device *device) >>>       value |= MIPI_CAL_CTRL_START; >>>       tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); >>>   -    err = tegra_mipi_wait(device->mipi); >> Doesn't MIPI clock need to be enabled during of the calibration process? > MIPI clock is already enabled in tegra_mipi_calibrate >> >>>       mutex_unlock(&device->mipi->lock); >>>       clk_disable(device->mipi->clk); What keeps MIPI clock enabled after completion of the tegra_mipi_calibrate() invocation? >>>   -    return err; >>> +    return 0; >>>   } >>>   EXPORT_SYMBOL(tegra_mipi_calibrate);