Re: [PATCH v2 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY

Bryan O'Donoghue
2025-10-17T10:55:57Z

On 17/10/2025 00:10, Vijay Kumar Tumati wrote:
>
> There are three offsets in the picture here wrt the CSIPHY instance base
> address
>
> 1. First offset to the common registers of the PHY, 'regs->offset' (that
> follows the lane registers)
>
> 2. Second offset to the status registers within the common registers .
> This has been historically the same and hard coded
> in 'CSIPHY_3PH_CMN_CSI_COMMON_STATUSn' to 0xb0 but this is now changing
> on Kaanapali.
>
> 3. Third set of offsets (12, 13, 14 and 15) are to the version registers
> within the status registers.
>
> This change merely generalizes the CSIPHY_3PH_CMN_CSI_COMMON_STATUSn
> macro for chip sets with different second offset using "regs-
> >common_status_offset". There should not be any impact to the other
> chip sets, for which it is set to the same 0xb0 in csiphy_init().
>
> Please advise if you still think it requires a patch series for itself
> and we can do that. Thanks.

This should be a separate patch yes.

---
bod