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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b87959c9763sm1330649066b.35.2026.01.20.05.18.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Jan 2026 05:18:25 -0800 (PST) Message-ID: Date: Tue, 20 Jan 2026 14:18:22 +0100 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible To: Krzysztof Kozlowski , Luca Weiss , Dmitry Baryshkov Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti , Bjorn Andersson , Konrad Dybcio , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260116-milos-cci-v1-0-28e01128da9c@fairphone.com> <20260116-milos-cci-v1-2-28e01128da9c@fairphone.com> <20260117-obedient-galago-from-eldorado-8e0ba4@quoll> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260117-obedient-galago-from-eldorado-8e0ba4@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 4JPfRBs23SHNWqtGHhzuXe-c2QGuTOyD X-Proofpoint-ORIG-GUID: 4JPfRBs23SHNWqtGHhzuXe-c2QGuTOyD X-Authority-Analysis: v=2.4 cv=LPBrgZW9 c=1 sm=1 tr=0 ts=696f80a4 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=6H0WHjuAAAAA:8 a=ezRqCCqFh2AFBysmAOIA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIwMDExMCBTYWx0ZWRfXxylNEqOTP2FL kLD3AXq9CrOPnyU8k5fWsEJ2LLIVhSWF6Gu2IZFyNGIcco1aCyZpv5SfDIhFSAPim7bpiO3tNK4 diIXzS2NAFgBC4dFY8SQZK6R2WLiJgjzK+GdnA8/lfMCDsaOzIY9hiU4tHZD75LgECvqTscCAtB 5ubZbgemARAYFHZRoLlTUaP3hCG5gFkukGk4egIbhjDGJPJhx4DWBssFD32jp9uNCJflqyjKaPM jlL5Y/HvTtPjeeIPPzCuaQ/RZ2u7V6kOtbg+A7GYR/FTCDv6MHQF56bdhPhG+hmwRNLyYhcDzR+ 0BmHzRCu6l+lzloyYj2jxoTop8Z2ZYILkH0GTVSk4aJPdqPhpGPlb6fguRO1KrgeBpnNO3qk8cl 2Lm5fpg7dkr0cOXNYJ1+m74q98qexslTXqGmPCbaTI7IdHdD4XEF8hFDr/U9+aye1tY0fIYk9TG PdEr/A/ZqXHpAmDQWWA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-20_03,2026-01-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601200110 On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote: > On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote: >> Add Milos compatible for the CAMSS CCI interfaces. >> >> Signed-off-by: Luca Weiss >> --- >> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> index a3fe1eea6aec..c57d81258fba 100644 >> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> @@ -27,6 +27,7 @@ properties: >> - items: >> - enum: >> - qcom,kaanapali-cci >> + - qcom,milos-cci >> - qcom,qcm2290-cci >> - qcom,sa8775p-cci >> - qcom,sc7280-cci >> @@ -263,6 +264,23 @@ allOf: >> - const: cpas_ahb >> - const: cci >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,milos-cci >> + then: >> + properties: >> + clocks: >> + minItems: 3 >> + maxItems: 3 >> + clock-names: >> + items: >> + - const: soc_ahb >> + - const: cpas_ahb >> + - const: cci > > Same comments as other discussion these days - I guess that soc_ahb > serves the same purpose as camnoc_axi, so this is just last entri in the > if:then: blocks. > > I really find this binding terrible - around six names for AHB - so I do > not want another combination... I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK clock ("cci" here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC). The CAMSS TOP doc (for Milos specifically, but I would assume there's a pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_AHB_CLK and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains most of the programmable IPs on there (notably not the CSIPHYs, at least not on this platform) It further mentions that GCC_SOC_AHB_CLK is required for *any* register access within CAMSS. Perhaps it sits right in front of the xNoC-to-CAMNoC interface. This only enforces my imagination of CAMSS being a fully contained "bus" (perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus).. +Dmitry, myself and a number of our colleagues were deliberating how to best represent the hardware going forward and I think we at some point waved the idea of putting every camera subdevice under a "camss: bus@ {}"-type node, which would hold the reference to the TITAN_TOP_GDSC. This seems fitting for housing the SOC_AHB clock as well and therefore concluding this discussion. Konrad