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Wed, 10 Sep 2025 03:57:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFd6cAY5KUWWKRCtZ5BO2LMkzPi8rG6m9xuEQDohogxbjye/JxfepADt3ID1u913pa8j6uKwQ== X-Received: by 2002:a05:6a00:92a5:b0:772:59d2:3a49 with SMTP id d2e1a72fcca58-7742dda745amr16974587b3a.13.1757501839259; Wed, 10 Sep 2025 03:57:19 -0700 (PDT) Received: from [10.217.219.207] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-775f4976bcasm2333665b3a.100.2025.09.10.03.57.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Sep 2025 03:57:18 -0700 (PDT) Message-ID: Date: Wed, 10 Sep 2025 16:27:12 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] Qualcomm CCI I2C clock requirements enforcement To: Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: KRADxIwIyXrPn4-Z_lh3zCD4qoVpjvyl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzNSBTYWx0ZWRfXwljhXJAm0JdS vfRtKd40IOPrTSPB1uG2znMkbBgY+xtvatL6YoLvU68XdDw38DSkB0p6Lk/nNUGsdkIn3/uDaGP aDlDI0knv7txHRCTF4peZ6ZHZUB1vkLgTZStwO7gd/JuP5SZxAyhH9jD0X/9ZX8G4IfYttujRf4 4JgiMT8AwnHhNVFFcIq3CQ5vuu+fXQ/+Sp3Be0vmcSaNsTtxw49Fboz+qORH/E86XCVEeNfPiQ3 FpvmbUIN4AQtL2QHAhMuKAlGrQ2OPsFcLR5D2eGkXUY4HsPbe1sOSQL/362jzlAHqJLGKRCdaMh obXecvcSwPlhYJvTlz+FCu0JUcf9WuCstHIp+VYOP7jCxwa4C5CkkUIeWWmSgn81FITdFGMIxfu NU+u9bQv X-Proofpoint-GUID: KRADxIwIyXrPn4-Z_lh3zCD4qoVpjvyl X-Authority-Analysis: v=2.4 cv=N8UpF39B c=1 sm=1 tr=0 ts=68c15990 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=3WXPGMdjBYCeSjfzpvMA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-09_03,2025-09-10_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060035 On 9/4/2025 8:01 PM, Konrad Dybcio wrote: > The hardware requires the faster of the two (37.5 MHz as opposed to > 19.2 MHz) clock rates to hit the required timings for I2C Fast+ Mode. Should mention "source clock rates" to not confuse with derived frequency/timings for Fast+ mode.> > Additionally, the magic presets for electrical tuning registers on SoCs > supporting that faster mode ("cci_v2" in the driver) are calculated are/is calculated> based on that faster frequency. > > Moreover, while its unlikely that it would ever exhibit as an issue > given CCI is a slow & tiny core, we do need to express a minimal voltage > level for any given clock rate, which is where the (optional - > backwards compat) OPP table addition comes in. > > This series helps ensure all these requirements are met. > > Patch 1 is a related but independent fix, can be picked right away > Patch 5 can be functionally merged as-is, but depends on patch 2 for > bindings > > Signed-off-by: Konrad Dybcio > --- > Konrad Dybcio (5): > arm64: dts: qcom: sc8280xp: Fix CCI3 interrupt > dt-bindings: i2c: qcom-cci: Allow operating-points-v2 > i2c: qcom-cci: Drop single-line wrappers > i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements > arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts > > .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 + > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 +++++++- > drivers/i2c/busses/i2c-qcom-cci.c | 45 +++++++++++++++++----- > 3 files changed, 52 insertions(+), 11 deletions(-) > --- > base-commit: 4ac65880ebca1b68495bd8704263b26c050ac010 > change-id: 20250904-topic-cci_updates-800fdc9bada4 > > Best regards,