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Mon, 02 Dec 2024 12:55:44 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B2CthV7021626 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 12:55:43 GMT Received: from [10.217.219.207] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 04:55:38 -0800 Message-ID: Date: Mon, 2 Dec 2024 18:25:35 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/4] dt-bindindgs: i2c: qcom,i2c-geni: Document shared flag To: Krzysztof Kozlowski , , , , , , , , , , , , , , , , , , CC: References: <20241129144357.2008465-1-quic_msavaliy@quicinc.com> <20241129144357.2008465-2-quic_msavaliy@quicinc.com> <75f2cc08-e3ab-41fb-aa94-22963c4ffd82@quicinc.com> <904ae8ea-d970-4b4b-a30a-cd1b65296a9b@kernel.org> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <904ae8ea-d970-4b4b-a30a-cd1b65296a9b@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XA6PMkdLBdJuYQISwDC-dpgvldnzt9NW X-Proofpoint-GUID: XA6PMkdLBdJuYQISwDC-dpgvldnzt9NW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=974 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412020113 On 12/2/2024 4:34 PM, Krzysztof Kozlowski wrote: > On 02/12/2024 11:38, Mukesh Kumar Savaliya wrote: >>> >>> Come with one flag or enum, if needed, covering all your cases like this. >>> >> Let me explain, this feature is one of the additional software case >> adding on base protocol support. if we dont have more than one usecase >> or repurposing this feature, why do we need to add enums ? I see one >> flag gpi_mode but it's internal to driver not exposed to user or expose >> any usecase/feature. >> >> Below was our earlier context, just wanted to add for clarity. >> -- >> > Is sharing of IP blocks going to be also for other devices? If yes, then >> > this should be one property for all Qualcomm devices. If not, then be >> > sure that this is the case because I will bring it up if you come with >> > one more solution for something else. > > > You keep repeating the same. You won't receive any other answer. > So far i was in context to SEs. I am not sure in qualcomm SOC all cores supporting this feature and if it at all it supports, it may have it's own mechanism then what is followed in SE IP. I was probably thinking on my owned IP core hence i was revolving around. Hope this dt-binding i can conclude somewhere by seeking answer from other IP core owners within qualcomm. >> > >> IP blocks like SE can be shared. Here we are talking about I2C sharing. >> In future it can be SPI sharing. But design wise it fits better to add >> flag per SE node. Same we shall be adding for SPI too in future. > > > How flag per SE node is relevant? I did not ask to move the property. > >> >> Please let me know your further suggestions. > We do not talk about I2C or SPI here only. We talk about entire SoC. > Since beginning. Find other patch proposals and align with rest of > Qualcomm developers so that you come with only one definition for this > feature/characteristic. Or do you want to say that I am free to NAK all > further properties duplicating this one? > > Please confirm that you Qualcomm engineers understand the last statement > and that every block will use se-shared, even if we speak about UFS for > example. This UFS word atleast makes me understand and gave me clarity that i need to talk to different IP owners within qualcomm and get an agreement for my i2c feature. I am not sure if there exist an usecase the way we are sharing for i2c. Also i don't know how we can make similar description if different cores and functionality are different. If you have heard from any other IP core, please keep some usecases/IP names. Since This demands internal discussion, so give me time to conclude how the IPs are shared and is it the similar to what i have developed here for I2C. (sorry that so far i was in context to my SE protocols/ IPs only). > > Best regards, > Krzysztof