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Thu, 08 Oct 2026 12:45:38 -0700 (PDT) X-Received: by 2002:a05:7301:5414:b0:352:2e10:10c3 with SMTP id 5a478bee46e88-3535f43829cmr468256eec.36.1791488738093; Thu, 08 Oct 2026 12:45:38 -0700 (PDT) Received: from [192.168.1.2] ([106.222.229.121]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537ca1b556sm277985eec.9.2026.10.08.12.45.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Oct 2026 12:45:37 -0700 (PDT) Message-ID: Date: Fri, 9 Oct 2026 01:15:29 +0530 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 6/9] spi: qcom-geni: Use geni_se_set_rate() for setting source clock frequency To: Praveen Talari , konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com> <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-6-091697dbeb02@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-6-091697dbeb02@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BfpNQbt2 c=1 sm=1 tr=0 ts=6ac7f2e4 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=soJen2uxB0ky/kNk6TDY8g==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=ld924GHQG9e8gPgwT3gA:9 a=QEXdDO2ut3YA:10 a=ZXulRonScM0A:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: ko58Xsjuo9zr9_s9ZPC7XGfuSvWItpiQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDA3OCBTYWx0ZWRfXzgT/fOs/fPdX 2Za+qCllWXpVlzds/MRxD9ya0oueJxloKwYq9QfYIdMIXBdbF51KYeGkv+yx0rSlSZkVC8z0qQM T7p8BTB0L1xQtx8AJaFkgsnx9NC0FlonKQRzOO8SE8k4fXz4Xwajr//7QYa5Pn7r6BfBCj3hHSB OWH2ctJ+lCEZ9LPA/FXqzVI218Si5xFXrvrIl8y7e+mVSjRIinldPVhtTeax6uWTLT3yw6jQ12t BrhgrAJX87pDTtK5u4DNw1DwNUYKfJfc/7KddFjmuagOhBPnjyWt0aloNjQ7RFrEQv5oigU3hf3 q25Glg6xe0jl/3HBxwBQx63aDJ/44EU4BJr5DnqVZ1BQNCX/dwb9MJa0e+l8J+mvjQAG1A9lgwE hR9VJvvGarfESuGQlxroruXi+lyMeXzJP1FX+bxnHoLi7ICdLJ9Le+DDFfeW6/jffpqB0v0ccmE 8H01erxKubpRQ7AQMlg== X-Proofpoint-GUID: ko58Xsjuo9zr9_s9ZPC7XGfuSvWItpiQ X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDA3OCBTYWx0ZWRfX/1Mci87CthW7 b0paAr5OiB2aYfjurG2Sjw8h87XOc1ptYissQwJUI2RvAVvSFVFj/uVqiVr4Iw83GQBT1/Zpv2e rUpiEeH26vQ8YkaG/4UHiPR0g1VZmYM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_06,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080078 On 8/27/2026 11:29 PM, Praveen Talari wrote: > On the SA8255P platform there is no Linux clock handler for the SE > source clock, so the driver has no way to look up the source clock > index and divider needed to fill the GSI CONFIG0 TRE for a requested > transfer frequency. To work around this, firmware instead exposes the > SE HW supported source clock frequencies as OPPs on the perf domain > device. > > geni_se_domain_attach() now populates clk_perf_tbl from > the performance-domain OPP table, allowing firmware-managed > platforms to use geni_se_clk_freq_match(). > > Use geni_se_set_rate() instead of dev_pm_opp_set_rate() > so clock programming is handled centrally by the GENI core, > independent of the underlying clock-control mechanism. > > Acked-by: Mark Brown > Signed-off-by: Praveen Talari > --- Reviewed-by: Mukesh Kumar Savaliya