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From: Dmitry Osipenko <digetx@gmail.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>,
	thierry.reding@gmail.com, jonathanh@nvidia.com,
	mkarthik@nvidia.com, smohammed@nvidia.com, talho@nvidia.com
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-i2c@vger.kernel.org
Subject: Re: [PATCH V15 6/6] i2c: tegra: add i2c interface timing support
Date: Fri, 8 Feb 2019 16:00:57 +0300	[thread overview]
Message-ID: <e86e3e79-ba21-b833-b458-c833eded6e5a@gmail.com> (raw)
In-Reply-To: <3824e7bd-e129-511a-358b-42391ccee0f9@gmail.com>

08.02.2019 15:53, Dmitry Osipenko пишет:
> 08.02.2019 0:47, Sowjanya Komatineni пишет:
>> This patch adds I2C interface timing registers support for
>> proper bus rate configuration along with meeting the I2C spec
>> setup and hold times based on the tuning performed on Tegra210,
>> Tegra186 and Tegra194 platforms.
>>
>> I2C_INTERFACE_TIMING_0 register contains TLOW and THIGH field
>> and Tegra I2C controller design uses them as a part of internal
>> clock divisor.
>>
>> I2C_INTERFACE_TIMING_1 register contains the setup and hold times
>> for start and stop conditions.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
> 
> [snip]
> 
>>  
>> +	if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
>> +	    i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) {
>> +		tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
>> +		thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
>> +		tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
>> +	} else {
>> +		tlow = i2c_dev->hw->tlow_std_mode;
>> +		thigh = i2c_dev->hw->thigh_std_mode;
>> +		tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
>> +	}
>> +
>> +	if (i2c_dev->hw->has_interface_timing_reg && val) {
> 
> Shouldn't it be "&& tlow"?

Ah, there is "thigh" in use here.. so it all just doesn't make sense since "&& val" is always true. 

> 
>> +		val = (thigh << I2C_THIGH_SHIFT) | tlow;
>> +		i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
>> +	}
>> +
>> +	if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
>> +		i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
> 
> Do we really need those "&& tlow" and "&& tsu_thd" at all? It looks to me that checking for "has_interface_timing_reg" should be enough.
> 

      reply	other threads:[~2019-02-08 13:00 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-07 21:47 [PATCH V15 1/6] i2c: tegra: sort all the include headers alphabetically Sowjanya Komatineni
2019-02-07 21:47 ` [PATCH V15 2/6] i2c: tegra: add bus clear Master Support Sowjanya Komatineni
2019-02-07 21:47 ` [PATCH V15 3/6] i2c: tegra: fix maximum transfer size Sowjanya Komatineni
2019-02-07 22:09   ` Dmitry Osipenko
2019-02-07 22:25     ` Dmitry Osipenko
2019-02-08 12:46       ` Dmitry Osipenko
2019-02-08 14:12         ` Peter Rosin
2019-02-08 14:32           ` Dmitry Osipenko
2019-02-08 15:25             ` Sowjanya Komatineni
2019-02-08 15:44               ` Dmitry Osipenko
2019-02-07 21:47 ` [PATCH V15 4/6] i2c: tegra: Add DMA support Sowjanya Komatineni
2019-02-08 12:47   ` Dmitry Osipenko
2019-02-08 15:49     ` Sowjanya Komatineni
2019-02-08 15:55       ` Sowjanya Komatineni
2019-02-08 15:58         ` Sowjanya Komatineni
2019-02-08 16:15           ` Dmitry Osipenko
2019-02-07 21:47 ` [PATCH V15 5/6] i2c: tegra: update transfer timeout Sowjanya Komatineni
2019-02-07 21:47 ` [PATCH V15 6/6] i2c: tegra: add i2c interface timing support Sowjanya Komatineni
2019-02-08 12:53   ` Dmitry Osipenko
2019-02-08 13:00     ` Dmitry Osipenko [this message]

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