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I looked at that ARM definition for READ_ONCE/WRITE_ONCE, and those didn't really look like they they addressed this kind of cross-core write visibility, it looked more like it was about avoiding read/write tearing. Read acquire and write release can sometimes replace explicit barrier instructions, but felt adding an explicit barrier was a simpler solution. If this were highly performance critical code, then the benefits of avoiding explicit barriers would be worth a lot more effort. I know the ARM Barrier docs at https://developer.arm.com/documentation/genc007826/latest/ have an example under "Sending Interrupts and Barriers", page 19, that is very specific that a DSB barrier is required in cases where you write to normal memory on one core and then trigger an interrupt, and the normal memory is read on another core. It explicitly says that even if a memory write to strongly ordered memory (device memory) triggers the interrupt, you would need a DSB barrier. That example seemed like a very good match with what the DW i2c driver was doing. I also found the video at https://www.youtube.com/watch?v=2I8OHacills had some useful explanations of when barriers are needed. It was a little puzzling in the video, it seemed to say a DMB barrier would be sufficient for this case, even though the ARM barrier docs say a DSB is needed. The DMB only stalls execution of memory accesses, the DSB stalls execution of all instructions. The Linux wmb macro is a DSB barrier on ARM. Jan