* [Patch V5 1/2] i2c: imx: add devicetree binding for lpi2c
From: Gao Pan @ 2016-11-21 7:51 UTC (permalink / raw)
To: wsa, u.kleine-koenig, cmo, robh, vz, wsa-dev
Cc: linux-i2c, pandy.gao, frank.li, fugang.duan
Add a binding document for lpi2c driver
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
---
.../devicetree/bindings/i2c/i2c-imx-lpi2c.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
new file mode 100644
index 0000000..70c054a
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
@@ -0,0 +1,20 @@
+* Freescale Low Power Inter IC (LPI2C) for i.MX
+
+Required properties:
+- compatible :
+ - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc
+ - "fsl,imx8dv-lpi2c" for LPI2C compatible with the one integrated on i.MX8DV soc
+- reg : address and length of the lpi2c master registers
+- interrupt-parent : core interrupt controller
+- interrupts : lpi2c interrupt
+- clocks : lpi2c clock specifier
+
+Examples:
+
+lpi2c7: lpi2c7@40A50000 {
+ compatible = "fsl,imx8dv-lpi2c";
+ reg = <0x40A50000 0x10000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_LPI2C7>;
+};
--
1.9.1
^ permalink raw reply related
* [PATCH] i2c: designware: add reset interface
From: Zhangfei Gao @ 2016-11-22 4:41 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-arm-kernel, linux-i2c, Zhangfei Gao
Some platforms like hi3660 need do reset first to allow accessing registers
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/i2c/busses/i2c-designware-core.h | 1 +
drivers/i2c/busses/i2c-designware-platdrv.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 0d44d2a..94b14fa 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -80,6 +80,7 @@ struct dw_i2c_dev {
void __iomem *base;
struct completion cmd_complete;
struct clk *clk;
+ struct reset_control *rst;
u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
struct dw_pci_controller *controller;
int cmd_err;
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 0b42a12..fd80e58 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -38,6 +38,7 @@
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/io.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/platform_data/i2c-designware.h>
@@ -176,6 +177,10 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
dev->irq = irq;
platform_set_drvdata(pdev, dev);
+ dev->rst = devm_reset_control_get(&pdev->dev, NULL);
+ if (!IS_ERR(dev->rst))
+ reset_control_reset(dev->rst);
+
/* fast mode by default because of legacy reasons */
dev->clk_freq = 400000;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v4 1/2] i2c: aspeed: added driver for Aspeed I2C
From: Cédric Le Goater @ 2016-11-22 6:40 UTC (permalink / raw)
To: Brendan Higgins, wsa-z923LK4zBo2bacvFa/9K2g,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, openbmc-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1478311099-6771-2-git-send-email-brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Hello Brendan,
A few comments below,
On 11/05/2016 02:58 AM, Brendan Higgins wrote:
> Added initial master and slave support for Aspeed I2C controller.
> Supports fourteen busses present in ast24xx and ast25xx BMC SoCs by
> Aspeed.
>
> Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> ---
> Changes for v2:
> - Added single module_init (multiple was breaking some builds).
> Changes for v3:
> - Removed "bus" device tree param; now extracted from bus address offset
> Changes for v4:
> - I2C adapter number is now generated dynamically unless specified in alias.
> ---
> drivers/i2c/busses/Kconfig | 10 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-aspeed.c | 807 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 818 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-aspeed.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index d252276..b6caa5d 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -1009,6 +1009,16 @@ config I2C_RCAR
> This driver can also be built as a module. If so, the module
> will be called i2c-rcar.
>
> +config I2C_ASPEED
> + tristate "Aspeed AST2xxx SoC I2C Controller"
> + depends on ARCH_ASPEED
> + help
> + If you say yes to this option, support will be included for the
> + Aspeed AST2xxx SoC I2C controller.
> +
> + This driver can also be built as a module. If so, the module
> + will be called i2c-aspeed.
> +
> comment "External I2C/SMBus adapter drivers"
>
> config I2C_DIOLAN_U2C
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 29764cc..826e780 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -99,6 +99,7 @@ obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
> obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
> obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
> obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
> +obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
>
> # External I2C/SMBus adapter drivers
> obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
> diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
> new file mode 100644
> index 0000000..88e078a
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-aspeed.c
> @@ -0,0 +1,807 @@
> +/*
> + * I2C adapter for the ASPEED I2C bus.
> + *
> + * Copyright (C) 2012-2020 ASPEED Technology Inc.
> + * Copyright 2016 IBM Corporation
> + * Copyright 2016 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/i2c.h>
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/errno.h>
> +#include <linux/interrupt.h>
> +#include <linux/completion.h>
> +#include <linux/slab.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +
> +/* I2C Register */
> +#define ASPEED_I2C_FUN_CTRL_REG 0x00
> +#define ASPEED_I2C_AC_TIMING_REG1 0x04
> +#define ASPEED_I2C_AC_TIMING_REG2 0x08
> +#define ASPEED_I2C_INTR_CTRL_REG 0x0c
> +#define ASPEED_I2C_INTR_STS_REG 0x10
> +#define ASPEED_I2C_CMD_REG 0x14
> +#define ASPEED_I2C_DEV_ADDR_REG 0x18
> +#define ASPEED_I2C_BYTE_BUF_REG 0x20
> +#define ASPEED_I2C_OFFSET_START 0x40
> +#define ASPEED_I2C_OFFSET_INCREMENT 0x40
> +
> +#define ASPEED_I2C_NUM_BUS 14
> +
> +/* Global Register Definition */
> +/* 0x00 : I2C Interrupt Status Register */
> +/* 0x08 : I2C Interrupt Target Assignment */
> +
> +/* Device Register Definition */
> +/* 0x00 : I2CD Function Control Register */
> +#define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
> +#define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
> +#define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
> +#define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
> +#define ASPEED_I2CD_SLAVE_EN BIT(1)
> +#define ASPEED_I2CD_MASTER_EN BIT(0)
> +
> +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */
> +#define ASPEED_NO_TIMEOUT_CTRL 0
> +
> +
> +/* 0x0c : I2CD Interrupt Control Register &
> + * 0x10 : I2CD Interrupt Status Register
> + *
> + * These share bit definitions, so use the same values for the enable &
> + * status bits.
> + */
> +#define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
> +#define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
> +#define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
> +#define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
> +#define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
> +#define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
> +#define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
> +#define ASPEED_I2CD_INTR_RX_DONE BIT(2)
> +#define ASPEED_I2CD_INTR_TX_NAK BIT(1)
> +#define ASPEED_I2CD_INTR_TX_ACK BIT(0)
> +
> +/* 0x14 : I2CD Command/Status Register */
> +#define ASPEED_I2CD_SCL_LINE_STS BIT(18)
> +#define ASPEED_I2CD_SDA_LINE_STS BIT(17)
> +#define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
> +#define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
> +
> +/* Command Bit */
> +#define ASPEED_I2CD_M_STOP_CMD BIT(5)
> +#define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
> +#define ASPEED_I2CD_M_RX_CMD BIT(3)
> +#define ASPEED_I2CD_S_TX_CMD BIT(2)
> +#define ASPEED_I2CD_M_TX_CMD BIT(1)
> +#define ASPEED_I2CD_M_START_CMD BIT(0)
> +
> +/* 0x18 : I2CD Slave Device Address Register */
> +#define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
> +
> +enum aspeed_i2c_slave_state {
> + ASPEED_I2C_SLAVE_START,
> + ASPEED_I2C_SLAVE_READ_REQUESTED,
> + ASPEED_I2C_SLAVE_READ_PROCESSED,
> + ASPEED_I2C_SLAVE_WRITE_REQUESTED,
> + ASPEED_I2C_SLAVE_WRITE_RECEIVED,
> + ASPEED_I2C_SLAVE_STOP,
> +};
> +
> +struct aspeed_i2c_bus {
> + struct i2c_adapter adap;
> + struct device *dev;
> + void __iomem *base;
> + spinlock_t lock;
> + struct completion cmd_complete;
> + int irq;
> + /* Transaction state. */
> + struct i2c_msg *msg;
> + int msg_pos;
> + u32 cmd_err;
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> + struct i2c_client *slave;
> + enum aspeed_i2c_slave_state slave_state;
> +#endif
> +};
> +
> +struct aspeed_i2c_controller {
> + struct device *dev;
> + void __iomem *base;
> + int irq;
> + struct irq_domain *irq_domain;
> +};
> +
> +static inline void aspeed_i2c_write(struct aspeed_i2c_bus *bus, u32 val,
> + u32 reg)
> +{
> + writel(val, bus->base + reg);
> +}
> +
> +static inline u32 aspeed_i2c_read(struct aspeed_i2c_bus *bus, u32 reg)
> +{
> + return readl(bus->base + reg);
> +}
> +
> +static u8 aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
> +{
> + u32 command;
> + unsigned long time_left;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + command = aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG);
> + /* Bus is idle: no recovery needed. */
> + if ((command & ASPEED_I2CD_SDA_LINE_STS) &&
> + (command & ASPEED_I2CD_SCL_LINE_STS))
> + goto out;
> +
> + dev_dbg(bus->dev, "bus hung (state %x), attempting recovery\n",
> + command);
> +
> + /* Bus held: put bus in stop state. */
> + if ((command & ASPEED_I2CD_SDA_LINE_STS) &&
> + !(command & ASPEED_I2CD_SCL_LINE_STS)) {
> + aspeed_i2c_write(bus, ASPEED_I2CD_M_STOP_CMD,
> + ASPEED_I2C_CMD_REG);
> + reinit_completion(&bus->cmd_complete);
> + spin_unlock_irqrestore(&bus->lock, flags);
> +
> + time_left = wait_for_completion_interruptible_timeout(
> + &bus->cmd_complete, bus->adap.timeout * HZ);
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + if (time_left == 0)
> + ret = -ETIMEDOUT;
> + else if (bus->cmd_err)
> + ret = -EIO;
> + /* Bus error. */
> + } else if (!(command & ASPEED_I2CD_SDA_LINE_STS)) {
> + aspeed_i2c_write(bus, ASPEED_I2CD_BUS_RECOVER_CMD,
> + ASPEED_I2C_CMD_REG);
> + reinit_completion(&bus->cmd_complete);
> + spin_unlock_irqrestore(&bus->lock, flags);
> +
> + time_left = wait_for_completion_interruptible_timeout(
> + &bus->cmd_complete, bus->adap.timeout * HZ);
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + if (time_left == 0)
> + ret = -ETIMEDOUT;
> + else if (bus->cmd_err)
> + ret = -EIO;
> + /* Recovery failed. */
> + else if (!(aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG) &
> + ASPEED_I2CD_SDA_LINE_STS))
> + ret = -EIO;
> + }
> +
> +out:
> + spin_unlock_irqrestore(&bus->lock, flags);
> + return ret;
> +}
> +
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus)
> +{
> + bool irq_handled = true;
> + u32 command;
> + u32 irq_status;
> + u32 status_ack = 0;
> + u8 value;
> + struct i2c_client *slave = bus->slave;
> +
> + spin_lock(&bus->lock);
> + if (!slave) {
> + irq_handled = false;
> + goto out;
> + }
> + command = aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG);
> + irq_status = aspeed_i2c_read(bus, ASPEED_I2C_INTR_STS_REG);
> +
> + /* Slave was requested, restart state machine. */
> + if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
> + status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH;
> + bus->slave_state = ASPEED_I2C_SLAVE_START;
> + }
> + /* Slave is not currently active, irq was for someone else. */
> + if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
> + irq_handled = false;
> + goto out;
> + }
> +
> + dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
> + irq_status, command);
> +
> + /* Slave was sent something. */
> + if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
> + value = aspeed_i2c_read(bus, ASPEED_I2C_BYTE_BUF_REG) >> 8;
> + /* Handle address frame. */
> + if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
> + if (value & 0x1)
> + bus->slave_state =
> + ASPEED_I2C_SLAVE_READ_REQUESTED;
> + else
> + bus->slave_state =
> + ASPEED_I2C_SLAVE_WRITE_REQUESTED;
> + }
> + status_ack |= ASPEED_I2CD_INTR_RX_DONE;
> + }
> +
> + /* Slave was asked to stop. */
> + if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
> + status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
> + bus->slave_state = ASPEED_I2C_SLAVE_STOP;
> + }
> + if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
> + status_ack |= ASPEED_I2CD_INTR_TX_NAK;
> + bus->slave_state = ASPEED_I2C_SLAVE_STOP;
> + }
> +
> + if (bus->slave_state == ASPEED_I2C_SLAVE_READ_REQUESTED) {
> + if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
> + dev_err(bus->dev, "Unexpected ACK on read request.\n");
> + bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
> +
> + i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
> + aspeed_i2c_write(bus, value, ASPEED_I2C_BYTE_BUF_REG);
> + aspeed_i2c_write(bus, ASPEED_I2CD_S_TX_CMD, ASPEED_I2C_CMD_REG);
> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
> + status_ack |= ASPEED_I2CD_INTR_TX_ACK;
> + if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
> + dev_err(bus->dev,
> + "Expected ACK after processed read.\n");
> + i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
> + aspeed_i2c_write(bus, value, ASPEED_I2C_BYTE_BUF_REG);
> + aspeed_i2c_write(bus, ASPEED_I2CD_S_TX_CMD, ASPEED_I2C_CMD_REG);
> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_WRITE_REQUESTED) {
> + bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
> + i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_WRITE_RECEIVED) {
> + i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
> + i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
> + }
> +
> + if (status_ack != irq_status)
> + dev_err(bus->dev,
> + "irq handled != irq. expected %x, but was %x\n",
> + irq_status, status_ack);
> + aspeed_i2c_write(bus, status_ack, ASPEED_I2C_INTR_STS_REG);
> +
> +out:
> + spin_unlock(&bus->lock);
> + return irq_handled;
> +}
> +#endif
> +
> +static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
> +{
> + const u32 errs = ASPEED_I2CD_INTR_ARBIT_LOSS |
> + ASPEED_I2CD_INTR_ABNORMAL |
> + ASPEED_I2CD_INTR_SCL_TIMEOUT |
> + ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
> + ASPEED_I2CD_INTR_TX_NAK;
> + u32 irq_status;
> +
> + spin_lock(&bus->lock);
> + irq_status = aspeed_i2c_read(bus, ASPEED_I2C_INTR_STS_REG);
> + bus->cmd_err = irq_status & errs;
> +
> + dev_dbg(bus->dev, "master irq status 0x%08x\n", irq_status);
> +
> + /* No message to transfer. */
> + if (bus->cmd_err ||
> + (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) ||
> + (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE)) {
> + complete(&bus->cmd_complete);
> + goto out;
> + } else if (!bus->msg || bus->msg_pos >= bus->msg->len)
> + goto out;
> +
> + if ((bus->msg->flags & I2C_M_RD) &&
> + (irq_status & ASPEED_I2CD_INTR_RX_DONE)) {
> + bus->msg->buf[bus->msg_pos++] = aspeed_i2c_read(
> + bus, ASPEED_I2C_BYTE_BUF_REG) >> 8;
> + if (bus->msg_pos + 1 < bus->msg->len)
> + aspeed_i2c_write(bus, ASPEED_I2CD_M_RX_CMD,
> + ASPEED_I2C_CMD_REG);
> + else if (bus->msg_pos < bus->msg->len)
> + aspeed_i2c_write(bus, ASPEED_I2CD_M_RX_CMD |
> + ASPEED_I2CD_M_S_RX_CMD_LAST,
> + ASPEED_I2C_CMD_REG);
> + } else if (!(bus->msg->flags & I2C_M_RD) &&
> + (irq_status & ASPEED_I2CD_INTR_TX_ACK)) {
> + aspeed_i2c_write(bus, bus->msg->buf[bus->msg_pos++],
> + ASPEED_I2C_BYTE_BUF_REG);
> + aspeed_i2c_write(bus, ASPEED_I2CD_M_TX_CMD, ASPEED_I2C_CMD_REG);
> + }
is it safe to start a new transaction when in a interrupt handler ?
> + /* Transmission complete: notify caller. */
> + if (bus->msg_pos >= bus->msg->len)
> + complete(&bus->cmd_complete);
> +out:
> + aspeed_i2c_write(bus, irq_status, ASPEED_I2C_INTR_STS_REG);
so this is clearing the interrupt status just after having started
a new transaction on the bus. It looks unsafe to me as it could
clear the status of the just started transaction.
> + spin_unlock(&bus->lock);
> + return true;
> +}
> +
> +static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
> +{
> + struct aspeed_i2c_bus *bus = dev_id;
> +
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> + if (aspeed_i2c_slave_irq(bus)) {
> + dev_dbg(bus->dev, "irq handled by slave.\n");
> + return IRQ_HANDLED;
> + }
> +#endif
> + if (aspeed_i2c_master_irq(bus)) {
> + dev_dbg(bus->dev, "irq handled by master.\n");
> + return IRQ_HANDLED;
> + }
> + dev_err(bus->dev, "irq not handled properly!\n");
> + return IRQ_HANDLED;
> +}
> +
> +static int aspeed_i2c_master_single_xfer(struct i2c_adapter *adap,
> + struct i2c_msg *msg)
> +{
> + struct aspeed_i2c_bus *bus = adap->algo_data;
> + unsigned long flags;
> + u8 slave_addr;
> + u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
> + int ret = msg->len;
> + unsigned long time_left;
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + bus->msg = msg;
> + bus->msg_pos = 0;
> + slave_addr = msg->addr << 1;
> + if (msg->flags & I2C_M_RD) {
> + slave_addr |= 1;
> + command |= ASPEED_I2CD_M_RX_CMD;
> + if (msg->len == 1)
> + command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
> + }
> + aspeed_i2c_write(bus, slave_addr, ASPEED_I2C_BYTE_BUF_REG);
> + aspeed_i2c_write(bus, command, ASPEED_I2C_CMD_REG);
> + reinit_completion(&bus->cmd_complete);
> + spin_unlock_irqrestore(&bus->lock, flags);
> +
> + time_left = wait_for_completion_interruptible_timeout(
> + &bus->cmd_complete, bus->adap.timeout * HZ * msg->len);
Why do you multiply by * msg->len ?
> + if (time_left == 0)
> + return -ETIMEDOUT;
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + if (bus->cmd_err)
> + ret = -EIO;
> + bus->msg = NULL;
> + spin_unlock_irqrestore(&bus->lock, flags);
> +
> + return ret;
> +}
> +
> +static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
> + struct i2c_msg *msgs, int num)
> +{
> + struct aspeed_i2c_bus *bus = adap->algo_data;
> + int ret;
> + int i;
> + unsigned long flags;
> + unsigned long time_left;
> +
> + /* If bus is busy, attempt recovery. We assume a single master
> + * environment.
> + */
> + if (aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG) &
> + ASPEED_I2CD_BUS_BUSY_STS) {
> + ret = aspeed_i2c_recover_bus(bus);
> + if (ret)
> + return ret;
> + }
> +
> + for (i = 0; i < num; i++) {
> + ret = aspeed_i2c_master_single_xfer(adap, &msgs[i]);
> + if (ret < 0)
> + break;
> + /* TODO: Support other forms of I2C protocol mangling. */
> + if (msgs[i].flags & I2C_M_STOP) {
> + spin_lock_irqsave(&bus->lock, flags);
> + aspeed_i2c_write(bus, ASPEED_I2CD_M_STOP_CMD,
> + ASPEED_I2C_CMD_REG);
> + reinit_completion(&bus->cmd_complete);
> + spin_unlock_irqrestore(&bus->lock, flags);
> +
> + time_left = wait_for_completion_interruptible_timeout(
> + &bus->cmd_complete,
> + bus->adap.timeout * HZ);
> + if (time_left == 0)
> + return -ETIMEDOUT;
> + }
> + }
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + aspeed_i2c_write(bus, ASPEED_I2CD_M_STOP_CMD, ASPEED_I2C_CMD_REG);
> + reinit_completion(&bus->cmd_complete);
> + spin_unlock_irqrestore(&bus->lock, flags);
> +
> + time_left = wait_for_completion_interruptible_timeout(
> + &bus->cmd_complete, bus->adap.timeout * HZ);
> + if (time_left == 0)
> + return -ETIMEDOUT;
> +
> + /* If nothing went wrong, return number of messages transferred. */
> + if (ret < 0)
> + return ret;
> + else
> + return i;
> +}
> +
> +static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
> +}
> +
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +static int aspeed_i2c_reg_slave(struct i2c_client *client)
> +{
> + struct aspeed_i2c_bus *bus;
> + unsigned long flags;
> + u32 addr_reg_val;
> + u32 func_ctrl_reg_val;
> +
> + bus = client->adapter->algo_data;
> + spin_lock_irqsave(&bus->lock, flags);
> + if (bus->slave) {
> + spin_unlock_irqrestore(&bus->lock, flags);
> + return -EINVAL;
> + }
> +
> + /* Set slave addr. */
> + addr_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_DEV_ADDR_REG);
> + addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
> + addr_reg_val |= client->addr & ASPEED_I2CD_DEV_ADDR_MASK;
> + aspeed_i2c_write(bus, addr_reg_val, ASPEED_I2C_DEV_ADDR_REG);
> +
> + /* Switch from master mode to slave mode. */
> + func_ctrl_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG);
> + func_ctrl_reg_val &= ~ASPEED_I2CD_MASTER_EN;
> + func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
> + aspeed_i2c_write(bus, func_ctrl_reg_val, ASPEED_I2C_FUN_CTRL_REG);
> +
> + bus->slave = client;
> + bus->slave_state = ASPEED_I2C_SLAVE_STOP;
> + spin_unlock_irqrestore(&bus->lock, flags);
> + return 0;
> +}
> +
> +static int aspeed_i2c_unreg_slave(struct i2c_client *client)
> +{
> + struct aspeed_i2c_bus *bus = client->adapter->algo_data;
> + unsigned long flags;
> + u32 func_ctrl_reg_val;
> +
> + spin_lock_irqsave(&bus->lock, flags);
> + if (!bus->slave) {
> + spin_unlock_irqrestore(&bus->lock, flags);
> + return -EINVAL;
> + }
> +
> + /* Switch from slave mode to master mode. */
> + func_ctrl_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG);
> + func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
> + func_ctrl_reg_val |= ASPEED_I2CD_MASTER_EN;
> + aspeed_i2c_write(bus, func_ctrl_reg_val, ASPEED_I2C_FUN_CTRL_REG);
> +
> + bus->slave = NULL;
> + spin_unlock_irqrestore(&bus->lock, flags);
> + return 0;
> +}
> +#endif
> +
> +static const struct i2c_algorithm aspeed_i2c_algo = {
> + .master_xfer = aspeed_i2c_master_xfer,
> + .functionality = aspeed_i2c_functionality,
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> + .reg_slave = aspeed_i2c_reg_slave,
> + .unreg_slave = aspeed_i2c_unreg_slave,
> +#endif
> +};
> +
> +static u32 aspeed_i2c_get_clk_reg_val(u32 divider_ratio)
> +{
> + unsigned int inc = 0, div;
> + u32 scl_low, scl_high, data;
> +
> + for (div = 0; divider_ratio >= 16; div++) {
> + inc |= (divider_ratio & 1);
> + divider_ratio >>= 1;
> + }
> + divider_ratio += inc;
> + scl_low = (divider_ratio >> 1) - 1;
> + scl_high = divider_ratio - scl_low - 2;
> + data = 0x77700300 | (scl_high << 16) | (scl_low << 12) | div;
> + return data;
> +}
> +
> +static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus,
> + struct platform_device *pdev)
> +{
> + struct clk *pclk;
> + u32 clk_freq;
> + u32 divider_ratio;
> + int ret;
> +
> + pclk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(pclk)) {
> + dev_err(&pdev->dev, "clk_get failed\n");
> + return PTR_ERR(pclk);
> + }
> + ret = of_property_read_u32(pdev->dev.of_node,
> + "clock-frequency", &clk_freq);
> + if (ret < 0) {
> + dev_err(&pdev->dev,
> + "Could not read clock-frequency property\n");
> + clk_freq = 100000;
> + }
> + divider_ratio = clk_get_rate(pclk) / clk_freq;
> + /* We just need the clock rate, we don't actually use the clk object. */
> + devm_clk_put(&pdev->dev, pclk);
> +
> + /* Set AC Timing */
> + if (clk_freq / 1000 > 400) {
> + aspeed_i2c_write(bus, aspeed_i2c_read(bus,
> + ASPEED_I2C_FUN_CTRL_REG) |
> + ASPEED_I2CD_M_HIGH_SPEED_EN |
> + ASPEED_I2CD_M_SDA_DRIVE_1T_EN |
> + ASPEED_I2CD_SDA_DRIVE_1T_EN,
> + ASPEED_I2C_FUN_CTRL_REG);
> +
> + aspeed_i2c_write(bus, 0x3, ASPEED_I2C_AC_TIMING_REG2);
> + aspeed_i2c_write(bus, aspeed_i2c_get_clk_reg_val(divider_ratio),
> + ASPEED_I2C_AC_TIMING_REG1);
> + } else {
> + aspeed_i2c_write(bus, aspeed_i2c_get_clk_reg_val(divider_ratio),
> + ASPEED_I2C_AC_TIMING_REG1);
> + aspeed_i2c_write(bus, ASPEED_NO_TIMEOUT_CTRL,
> + ASPEED_I2C_AC_TIMING_REG2);
> + }
> +
> + return 0;
> +}
> +
> +static void noop(struct irq_data *data) { }
> +
> +static struct irq_chip aspeed_i2c_irqchip = {
> + .name = "ast-i2c",
> + .irq_unmask = noop,
> + .irq_mask = noop,
> +};
> +
> +static int aspeed_i2c_probe_bus(struct platform_device *pdev)
> +{
> + struct aspeed_i2c_bus *bus;
> + struct aspeed_i2c_controller *controller =
> + dev_get_drvdata(pdev->dev.parent);
> + struct resource *res;
> + int ret, irq;
> + u32 hwirq;
> +
> + bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
> + if (!bus)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + bus->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(bus->base))
> + return PTR_ERR(bus->base);
> +
> + bus->irq = platform_get_irq(pdev, 0);
> + if (bus->irq < 0)
> + return -ENXIO;
> + ret = of_property_read_u32(pdev->dev.of_node, "interrupts", &hwirq);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "no I2C 'interrupts' property\n");
> + return -ENXIO;
> + }
> + irq = irq_create_mapping(controller->irq_domain, hwirq);
> + irq_set_chip_data(irq, controller);
> + irq_set_chip_and_handler(irq, &aspeed_i2c_irqchip, handle_simple_irq);
> + ret = devm_request_irq(&pdev->dev, bus->irq, aspeed_i2c_bus_irq,
> + 0, dev_name(&pdev->dev), bus);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request interrupt\n");
> + return -ENXIO;
> + }
> +
> + /* Initialize the I2C adapter */
> + spin_lock_init(&bus->lock);
> + init_completion(&bus->cmd_complete);
> + bus->adap.owner = THIS_MODULE;
> + bus->adap.retries = 0;
> + bus->adap.timeout = 5;
> + bus->adap.algo = &aspeed_i2c_algo;
> + bus->adap.algo_data = bus;
> + bus->adap.dev.parent = &pdev->dev;
> + bus->adap.dev.of_node = pdev->dev.of_node;
> + snprintf(bus->adap.name, sizeof(bus->adap.name), "Aspeed i2c");
> +
> + bus->dev = &pdev->dev;
> +
> + /* reset device: disable master & slave functions */
> + aspeed_i2c_write(bus, 0, ASPEED_I2C_FUN_CTRL_REG);
> +
> + ret = aspeed_i2c_init_clk(bus, pdev);
> + if (ret < 0)
> + return ret;
> +
> + /* Enable Master Mode */
> + aspeed_i2c_write(bus, aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG) |
> + ASPEED_I2CD_MASTER_EN |
> + ASPEED_I2CD_MULTI_MASTER_DIS, ASPEED_I2C_FUN_CTRL_REG);
> +
> + /* Set interrupt generation of I2C controller */
> + aspeed_i2c_write(bus, ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
> + ASPEED_I2CD_INTR_BUS_RECOVER_DONE |
> + ASPEED_I2CD_INTR_SCL_TIMEOUT |
> + ASPEED_I2CD_INTR_ABNORMAL |
> + ASPEED_I2CD_INTR_NORMAL_STOP |
> + ASPEED_I2CD_INTR_ARBIT_LOSS |
> + ASPEED_I2CD_INTR_RX_DONE |
> + ASPEED_I2CD_INTR_TX_NAK |
> + ASPEED_I2CD_INTR_TX_ACK,
> + ASPEED_I2C_INTR_CTRL_REG);
> +
> + ret = i2c_add_adapter(&bus->adap);
> + if (ret < 0)
> + return -ENXIO;
> +
> + platform_set_drvdata(pdev, bus);
> +
> + dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
> + bus->adap.nr, bus->irq);
> +
> + return 0;
> +}
> +
> +static int aspeed_i2c_remove_bus(struct platform_device *pdev)
> +{
> + struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
> +
> + i2c_del_adapter(&bus->adap);
> + return 0;
> +}
> +
> +static const struct of_device_id aspeed_i2c_bus_of_table[] = {
> + { .compatible = "aspeed,ast2400-i2c-bus", },
> + { .compatible = "aspeed,ast2500-i2c-bus", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
> +
> +static struct platform_driver aspeed_i2c_bus_driver = {
> + .probe = aspeed_i2c_probe_bus,
> + .remove = aspeed_i2c_remove_bus,
> + .driver = {
> + .name = "ast-i2c-bus",
> + .of_match_table = aspeed_i2c_bus_of_table,
> + },
> +};
> +
> +static void aspeed_i2c_controller_irq(struct irq_desc *desc)
> +{
> + struct aspeed_i2c_controller *c = irq_desc_get_handler_data(desc);
> + unsigned long p, status;
> + unsigned int bus_irq;
> +
> + status = readl(c->base);
> + for_each_set_bit(p, &status, ASPEED_I2C_NUM_BUS) {
> + bus_irq = irq_find_mapping(c->irq_domain, p);
> + generic_handle_irq(bus_irq);
> + }
> +}
> +
> +static int aspeed_i2c_probe_controller(struct platform_device *pdev)
> +{
> + struct aspeed_i2c_controller *controller;
> + struct device_node *np;
> + struct resource *res;
> +
> + controller = kzalloc(sizeof(*controller), GFP_KERNEL);
use devm_kzalloc() may be ?
C.
> + if (!controller)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + controller->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(controller->base))
> + return PTR_ERR(controller->base);
> +
> + controller->irq = platform_get_irq(pdev, 0);
> + if (controller->irq < 0)
> + return -ENXIO;
> +
> + controller->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
> + ASPEED_I2C_NUM_BUS, &irq_domain_simple_ops, NULL);
> + if (!controller->irq_domain)
> + return -ENXIO;
> + controller->irq_domain->name = "ast-i2c-domain";
> +
> + irq_set_chained_handler_and_data(controller->irq,
> + aspeed_i2c_controller_irq, controller);
> +
> + controller->dev = &pdev->dev;
> +
> + platform_set_drvdata(pdev, controller);
> +
> + dev_info(controller->dev, "i2c controller registered, irq %d\n",
> + controller->irq);
> +
> + for_each_child_of_node(pdev->dev.of_node, np) {
> + of_platform_device_create(np, NULL, &pdev->dev);
> + of_node_put(np);
> + }
> +
> + return 0;
> +}
> +
> +static int aspeed_i2c_remove_controller(struct platform_device *pdev)
> +{
> + struct aspeed_i2c_controller *controller = platform_get_drvdata(pdev);
> +
> + irq_domain_remove(controller->irq_domain);
> + return 0;
> +}
> +
> +static const struct of_device_id aspeed_i2c_controller_of_table[] = {
> + { .compatible = "aspeed,ast2400-i2c-controller", },
> + { .compatible = "aspeed,ast2500-i2c-controller", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, aspeed_i2c_controller_of_table);
> +
> +static struct platform_driver aspeed_i2c_controller_driver = {
> + .probe = aspeed_i2c_probe_controller,
> + .remove = aspeed_i2c_remove_controller,
> + .driver = {
> + .name = "ast-i2c-controller",
> + .of_match_table = aspeed_i2c_controller_of_table,
> + },
> +};
> +
> +static int __init aspeed_i2c_driver_init(void)
> +{
> + int ret;
> +
> + ret = platform_driver_register(&aspeed_i2c_controller_driver);
> + if (ret < 0)
> + return ret;
> + return platform_driver_register(&aspeed_i2c_bus_driver);
> +}
> +module_init(aspeed_i2c_driver_init);
> +
> +static void __exit aspeed_i2c_driver_exit(void)
> +{
> + platform_driver_unregister(&aspeed_i2c_bus_driver);
> + platform_driver_unregister(&aspeed_i2c_controller_driver);
> +}
> +module_exit(aspeed_i2c_driver_exit);
> +
> +MODULE_AUTHOR("Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>");
> +MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
> +MODULE_LICENSE("GPL");
>
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^ permalink raw reply
* Re: [PATCH v5 6/6] i2c: use an IRQ to report Host Notify events, not alert
From: Wolfram Sang @ 2016-11-22 11:49 UTC (permalink / raw)
To: Benjamin Tissoires
Cc: Wolfram Sang, Dmitry Torokhov, linux-i2c, linux-kernel,
Jean Delvare
In-Reply-To: <20161121105248.GH2119@mail.corp.redhat.com>
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On Mon, Nov 21, 2016 at 11:52:48AM +0100, Benjamin Tissoires wrote:
> Hi Wolfram,
>
> On Nov 07 2016 or thereabouts, Wolfram Sang wrote:
> > On Thu, Oct 13, 2016 at 02:10:40PM +0200, Benjamin Tissoires wrote:
> > > The current SMBus Host Notify implementation relies on .alert() to
> > > relay its notifications. However, the use cases where SMBus Host
> > > Notify is needed currently is to signal data ready on touchpads.
> > >
> > > This is closer to an IRQ than a custom API through .alert().
> > > Given that the 2 touchpad manufacturers (Synaptics and Elan) that
> > > use SMBus Host Notify don't put any data in the SMBus payload, the
> > > concept actually matches one to one.
> >
> > I see the advantages. The only question I have: What if we encounter
> > devices in the future which do put data in the payload? Can this
> > mechanism be extended to handle that?
>
> I guess I haven't convinced you with my answer. Is there anything I can
> do to get this series in v4.10 or do you prefer waiting for v4.11?
I consider this v4.10 material. I was thinking a little about how to not
lose data with consecutive interrupts but then -EBUSY came along.
Nonetheless, it looks to me like the proper path to follow...
Thanks,
Wolfram
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^ permalink raw reply
* Re: [PATCH v2 0/3] i2c: octeon: thunder: Fix i2c not working on Octeon
From: Wolfram Sang @ 2016-11-22 12:01 UTC (permalink / raw)
To: Steven J. Hill
Cc: Jan Glauber, Wolfram Sang, linux-i2c, linux-mips, Paul Burton,
David Daney
In-Reply-To: <99500824-4c63-b769-ad66-c136529b14b2@cavium.com>
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On Mon, Nov 14, 2016 at 01:53:40PM -0600, Steven J. Hill wrote:
> On 11/14/2016 12:50 PM, Jan Glauber wrote:
> >
> > Since time is running out for 4.9 (or might have already if you're not
> > going to send another pull request) I'm going for the safe option
> > to fix the Octeon i2c problems, which is:
> >
> > 1. Reverting the readq_poll_timeout patch since it is broken
> > 2. Apply Patch #2 from Paul
> > 3. Add a small fix for the recovery that makes Paul's patch
> > work on ThunderX
> >
> > I'll try to come up with a better solution for 4.10. My plan is to get rid
> > of the polling-around-interrupt thing completely, but for that we need more
> > time to make it work on Octeon.
> >
> > Please consider for 4.9.
> >
> Hey Jan.
>
> This does not work on Octeon 71xx platforms. I will look at it more
> closely tomorrow.
What's the outcome here? It seems we want a bugfix for 4.9 but this
report keeps me reluctant to apply the series.
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^ permalink raw reply
* Re: [PATCH v2 0/3] i2c: octeon: thunder: Fix i2c not working on Octeon
From: Jan Glauber @ 2016-11-22 14:55 UTC (permalink / raw)
To: Steven J. Hill
Cc: Wolfram Sang, linux-i2c, linux-mips, Paul Burton, David Daney
In-Reply-To: <20161122120106.GB3993@katana>
On Tue, Nov 22, 2016 at 01:01:06PM +0100, Wolfram Sang wrote:
> On Mon, Nov 14, 2016 at 01:53:40PM -0600, Steven J. Hill wrote:
> > On 11/14/2016 12:50 PM, Jan Glauber wrote:
> > >
> > > Since time is running out for 4.9 (or might have already if you're not
> > > going to send another pull request) I'm going for the safe option
> > > to fix the Octeon i2c problems, which is:
> > >
> > > 1. Reverting the readq_poll_timeout patch since it is broken
> > > 2. Apply Patch #2 from Paul
> > > 3. Add a small fix for the recovery that makes Paul's patch
> > > work on ThunderX
> > >
> > > I'll try to come up with a better solution for 4.10. My plan is to get rid
> > > of the polling-around-interrupt thing completely, but for that we need more
> > > time to make it work on Octeon.
> > >
> > > Please consider for 4.9.
> > >
> > Hey Jan.
> >
> > This does not work on Octeon 71xx platforms. I will look at it more
> > closely tomorrow.
>
> What's the outcome here? It seems we want a bugfix for 4.9 but this
> report keeps me reluctant to apply the series.
>
Steven, did you have a chance to check which of the patches makes
Octeon 71xx fail?
--Jan
^ permalink raw reply
* Re: [PATCH v4 1/2] i2c: aspeed: added driver for Aspeed I2C
From: Kachalov Anton @ 2016-11-22 18:23 UTC (permalink / raw)
To: Cédric Le Goater, Brendan Higgins,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
openbmc-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <28078e6d-f5e4-da59-e226-baa9a60a4b19-Bxea+6Xhats@public.gmane.org>
Hello.
I would like to add my five cents here. Do not limit the bus_clk with 400kHz (FM) while HighSpeed is above 1MHz (above FM+ devices). I've successfully tested FM+ (1Mhz) in a quite big i2c network (a number of pca9600, pca9675, pca9848) with at least eight AST2150 SoCs on the common bus.
BTW. Just a lame question. If the device isn't designed to work on the higher speed (like standard of FM) while the bus selected as FM+, would those kind of devices just unoperate or may have undefined behavior and disturb the SDA/SCL? Just wondering to dynamically slowdown down to 100Khz (if needed) for the specific slave, but keep high rate (FM+) at the normal operation.
--- source/drivers/i2c/busses/i2c-aspeed.c.orig 2016-11-18 19:17:41.000000000 +0300
+++ source/drivers/i2c/busses/i2c-aspeed.c 2016-11-18 19:17:49.682092658 +0300
@@ -310,7 +310,7 @@ static void ast_i2c_dev_init(struct ast_
bus->bus_clk, clk_get_rate(bus->pclk));
/* Set AC Timing */
- if(bus->bus_clk / 1000 > 400) {
+ if(bus->bus_clk / 1000 > 1000) {
ast_i2c_write(bus, ast_i2c_read(bus, I2C_FUN_CTRL_REG) |
AST_I2CD_M_HIGH_SPEED_EN |
AST_I2CD_M_SDA_DRIVE_1T_EN |
22.11.2016, 12:07, "Cédric Le Goater" <clg-Bxea+6Xhats@public.gmane.org>:
> Hello Brendan,
>
> A few comments below,
>
> On 11/05/2016 02:58 AM, Brendan Higgins wrote:
>> Added initial master and slave support for Aspeed I2C controller.
>> Supports fourteen busses present in ast24xx and ast25xx BMC SoCs by
>> Aspeed.
>>
>> Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
>> ---
>> Changes for v2:
>> - Added single module_init (multiple was breaking some builds).
>> Changes for v3:
>> - Removed "bus" device tree param; now extracted from bus address offset
>> Changes for v4:
>> - I2C adapter number is now generated dynamically unless specified in alias.
>> ---
>> drivers/i2c/busses/Kconfig | 10 +
>> drivers/i2c/busses/Makefile | 1 +
>> drivers/i2c/busses/i2c-aspeed.c | 807 ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 818 insertions(+)
>> create mode 100644 drivers/i2c/busses/i2c-aspeed.c
>>
>> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
>> index d252276..b6caa5d 100644
>> --- a/drivers/i2c/busses/Kconfig
>> +++ b/drivers/i2c/busses/Kconfig
>> @@ -1009,6 +1009,16 @@ config I2C_RCAR
>> This driver can also be built as a module. If so, the module
>> will be called i2c-rcar.
>>
>> +config I2C_ASPEED
>> + tristate "Aspeed AST2xxx SoC I2C Controller"
>> + depends on ARCH_ASPEED
>> + help
>> + If you say yes to this option, support will be included for the
>> + Aspeed AST2xxx SoC I2C controller.
>> +
>> + This driver can also be built as a module. If so, the module
>> + will be called i2c-aspeed.
>> +
>> comment "External I2C/SMBus adapter drivers"
>>
>> config I2C_DIOLAN_U2C
>> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
>> index 29764cc..826e780 100644
>> --- a/drivers/i2c/busses/Makefile
>> +++ b/drivers/i2c/busses/Makefile
>> @@ -99,6 +99,7 @@ obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
>> obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
>> obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
>> obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
>> +obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
>>
>> # External I2C/SMBus adapter drivers
>> obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
>> diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
>> new file mode 100644
>> index 0000000..88e078a
>> --- /dev/null
>> +++ b/drivers/i2c/busses/i2c-aspeed.c
>> @@ -0,0 +1,807 @@
>> +/*
>> + * I2C adapter for the ASPEED I2C bus.
>> + *
>> + * Copyright (C) 2012-2020 ASPEED Technology Inc.
>> + * Copyright 2016 IBM Corporation
>> + * Copyright 2016 Google, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/i2c.h>
>> +#include <linux/irq.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/errno.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/completion.h>
>> +#include <linux/slab.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/err.h>
>> +#include <linux/clk.h>
>> +
>> +/* I2C Register */
>> +#define ASPEED_I2C_FUN_CTRL_REG 0x00
>> +#define ASPEED_I2C_AC_TIMING_REG1 0x04
>> +#define ASPEED_I2C_AC_TIMING_REG2 0x08
>> +#define ASPEED_I2C_INTR_CTRL_REG 0x0c
>> +#define ASPEED_I2C_INTR_STS_REG 0x10
>> +#define ASPEED_I2C_CMD_REG 0x14
>> +#define ASPEED_I2C_DEV_ADDR_REG 0x18
>> +#define ASPEED_I2C_BYTE_BUF_REG 0x20
>> +#define ASPEED_I2C_OFFSET_START 0x40
>> +#define ASPEED_I2C_OFFSET_INCREMENT 0x40
>> +
>> +#define ASPEED_I2C_NUM_BUS 14
>> +
>> +/* Global Register Definition */
>> +/* 0x00 : I2C Interrupt Status Register */
>> +/* 0x08 : I2C Interrupt Target Assignment */
>> +
>> +/* Device Register Definition */
>> +/* 0x00 : I2CD Function Control Register */
>> +#define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
>> +#define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
>> +#define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
>> +#define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
>> +#define ASPEED_I2CD_SLAVE_EN BIT(1)
>> +#define ASPEED_I2CD_MASTER_EN BIT(0)
>> +
>> +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */
>> +#define ASPEED_NO_TIMEOUT_CTRL 0
>> +
>> +
>> +/* 0x0c : I2CD Interrupt Control Register &
>> + * 0x10 : I2CD Interrupt Status Register
>> + *
>> + * These share bit definitions, so use the same values for the enable &
>> + * status bits.
>> + */
>> +#define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
>> +#define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
>> +#define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
>> +#define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
>> +#define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
>> +#define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
>> +#define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
>> +#define ASPEED_I2CD_INTR_RX_DONE BIT(2)
>> +#define ASPEED_I2CD_INTR_TX_NAK BIT(1)
>> +#define ASPEED_I2CD_INTR_TX_ACK BIT(0)
>> +
>> +/* 0x14 : I2CD Command/Status Register */
>> +#define ASPEED_I2CD_SCL_LINE_STS BIT(18)
>> +#define ASPEED_I2CD_SDA_LINE_STS BIT(17)
>> +#define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
>> +#define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
>> +
>> +/* Command Bit */
>> +#define ASPEED_I2CD_M_STOP_CMD BIT(5)
>> +#define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
>> +#define ASPEED_I2CD_M_RX_CMD BIT(3)
>> +#define ASPEED_I2CD_S_TX_CMD BIT(2)
>> +#define ASPEED_I2CD_M_TX_CMD BIT(1)
>> +#define ASPEED_I2CD_M_START_CMD BIT(0)
>> +
>> +/* 0x18 : I2CD Slave Device Address Register */
>> +#define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
>> +
>> +enum aspeed_i2c_slave_state {
>> + ASPEED_I2C_SLAVE_START,
>> + ASPEED_I2C_SLAVE_READ_REQUESTED,
>> + ASPEED_I2C_SLAVE_READ_PROCESSED,
>> + ASPEED_I2C_SLAVE_WRITE_REQUESTED,
>> + ASPEED_I2C_SLAVE_WRITE_RECEIVED,
>> + ASPEED_I2C_SLAVE_STOP,
>> +};
>> +
>> +struct aspeed_i2c_bus {
>> + struct i2c_adapter adap;
>> + struct device *dev;
>> + void __iomem *base;
>> + spinlock_t lock;
>> + struct completion cmd_complete;
>> + int irq;
>> + /* Transaction state. */
>> + struct i2c_msg *msg;
>> + int msg_pos;
>> + u32 cmd_err;
>> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
>> + struct i2c_client *slave;
>> + enum aspeed_i2c_slave_state slave_state;
>> +#endif
>> +};
>> +
>> +struct aspeed_i2c_controller {
>> + struct device *dev;
>> + void __iomem *base;
>> + int irq;
>> + struct irq_domain *irq_domain;
>> +};
>> +
>> +static inline void aspeed_i2c_write(struct aspeed_i2c_bus *bus, u32 val,
>> + u32 reg)
>> +{
>> + writel(val, bus->base + reg);
>> +}
>> +
>> +static inline u32 aspeed_i2c_read(struct aspeed_i2c_bus *bus, u32 reg)
>> +{
>> + return readl(bus->base + reg);
>> +}
>> +
>> +static u8 aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
>> +{
>> + u32 command;
>> + unsigned long time_left;
>> + unsigned long flags;
>> + int ret = 0;
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + command = aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG);
>> + /* Bus is idle: no recovery needed. */
>> + if ((command & ASPEED_I2CD_SDA_LINE_STS) &&
>> + (command & ASPEED_I2CD_SCL_LINE_STS))
>> + goto out;
>> +
>> + dev_dbg(bus->dev, "bus hung (state %x), attempting recovery\n",
>> + command);
>> +
>> + /* Bus held: put bus in stop state. */
>> + if ((command & ASPEED_I2CD_SDA_LINE_STS) &&
>> + !(command & ASPEED_I2CD_SCL_LINE_STS)) {
>> + aspeed_i2c_write(bus, ASPEED_I2CD_M_STOP_CMD,
>> + ASPEED_I2C_CMD_REG);
>> + reinit_completion(&bus->cmd_complete);
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> +
>> + time_left = wait_for_completion_interruptible_timeout(
>> + &bus->cmd_complete, bus->adap.timeout * HZ);
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + if (time_left == 0)
>> + ret = -ETIMEDOUT;
>> + else if (bus->cmd_err)
>> + ret = -EIO;
>> + /* Bus error. */
>> + } else if (!(command & ASPEED_I2CD_SDA_LINE_STS)) {
>> + aspeed_i2c_write(bus, ASPEED_I2CD_BUS_RECOVER_CMD,
>> + ASPEED_I2C_CMD_REG);
>> + reinit_completion(&bus->cmd_complete);
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> +
>> + time_left = wait_for_completion_interruptible_timeout(
>> + &bus->cmd_complete, bus->adap.timeout * HZ);
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + if (time_left == 0)
>> + ret = -ETIMEDOUT;
>> + else if (bus->cmd_err)
>> + ret = -EIO;
>> + /* Recovery failed. */
>> + else if (!(aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG) &
>> + ASPEED_I2CD_SDA_LINE_STS))
>> + ret = -EIO;
>> + }
>> +
>> +out:
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> + return ret;
>> +}
>> +
>> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
>> +static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus)
>> +{
>> + bool irq_handled = true;
>> + u32 command;
>> + u32 irq_status;
>> + u32 status_ack = 0;
>> + u8 value;
>> + struct i2c_client *slave = bus->slave;
>> +
>> + spin_lock(&bus->lock);
>> + if (!slave) {
>> + irq_handled = false;
>> + goto out;
>> + }
>> + command = aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG);
>> + irq_status = aspeed_i2c_read(bus, ASPEED_I2C_INTR_STS_REG);
>> +
>> + /* Slave was requested, restart state machine. */
>> + if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
>> + status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH;
>> + bus->slave_state = ASPEED_I2C_SLAVE_START;
>> + }
>> + /* Slave is not currently active, irq was for someone else. */
>> + if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
>> + irq_handled = false;
>> + goto out;
>> + }
>> +
>> + dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
>> + irq_status, command);
>> +
>> + /* Slave was sent something. */
>> + if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
>> + value = aspeed_i2c_read(bus, ASPEED_I2C_BYTE_BUF_REG) >> 8;
>> + /* Handle address frame. */
>> + if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
>> + if (value & 0x1)
>> + bus->slave_state =
>> + ASPEED_I2C_SLAVE_READ_REQUESTED;
>> + else
>> + bus->slave_state =
>> + ASPEED_I2C_SLAVE_WRITE_REQUESTED;
>> + }
>> + status_ack |= ASPEED_I2CD_INTR_RX_DONE;
>> + }
>> +
>> + /* Slave was asked to stop. */
>> + if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
>> + status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
>> + bus->slave_state = ASPEED_I2C_SLAVE_STOP;
>> + }
>> + if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
>> + status_ack |= ASPEED_I2CD_INTR_TX_NAK;
>> + bus->slave_state = ASPEED_I2C_SLAVE_STOP;
>> + }
>> +
>> + if (bus->slave_state == ASPEED_I2C_SLAVE_READ_REQUESTED) {
>> + if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
>> + dev_err(bus->dev, "Unexpected ACK on read request.\n");
>> + bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
>> +
>> + i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
>> + aspeed_i2c_write(bus, value, ASPEED_I2C_BYTE_BUF_REG);
>> + aspeed_i2c_write(bus, ASPEED_I2CD_S_TX_CMD, ASPEED_I2C_CMD_REG);
>> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
>> + status_ack |= ASPEED_I2CD_INTR_TX_ACK;
>> + if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
>> + dev_err(bus->dev,
>> + "Expected ACK after processed read.\n");
>> + i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
>> + aspeed_i2c_write(bus, value, ASPEED_I2C_BYTE_BUF_REG);
>> + aspeed_i2c_write(bus, ASPEED_I2CD_S_TX_CMD, ASPEED_I2C_CMD_REG);
>> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_WRITE_REQUESTED) {
>> + bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
>> + i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
>> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_WRITE_RECEIVED) {
>> + i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
>> + } else if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
>> + i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
>> + }
>> +
>> + if (status_ack != irq_status)
>> + dev_err(bus->dev,
>> + "irq handled != irq. expected %x, but was %x\n",
>> + irq_status, status_ack);
>> + aspeed_i2c_write(bus, status_ack, ASPEED_I2C_INTR_STS_REG);
>> +
>> +out:
>> + spin_unlock(&bus->lock);
>> + return irq_handled;
>> +}
>> +#endif
>> +
>> +static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
>> +{
>> + const u32 errs = ASPEED_I2CD_INTR_ARBIT_LOSS |
>> + ASPEED_I2CD_INTR_ABNORMAL |
>> + ASPEED_I2CD_INTR_SCL_TIMEOUT |
>> + ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
>> + ASPEED_I2CD_INTR_TX_NAK;
>> + u32 irq_status;
>> +
>> + spin_lock(&bus->lock);
>> + irq_status = aspeed_i2c_read(bus, ASPEED_I2C_INTR_STS_REG);
>> + bus->cmd_err = irq_status & errs;
>> +
>> + dev_dbg(bus->dev, "master irq status 0x%08x\n", irq_status);
>> +
>> + /* No message to transfer. */
>> + if (bus->cmd_err ||
>> + (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) ||
>> + (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE)) {
>> + complete(&bus->cmd_complete);
>> + goto out;
>> + } else if (!bus->msg || bus->msg_pos >= bus->msg->len)
>> + goto out;
>> +
>> + if ((bus->msg->flags & I2C_M_RD) &&
>> + (irq_status & ASPEED_I2CD_INTR_RX_DONE)) {
>> + bus->msg->buf[bus->msg_pos++] = aspeed_i2c_read(
>> + bus, ASPEED_I2C_BYTE_BUF_REG) >> 8;
>> + if (bus->msg_pos + 1 < bus->msg->len)
>> + aspeed_i2c_write(bus, ASPEED_I2CD_M_RX_CMD,
>> + ASPEED_I2C_CMD_REG);
>> + else if (bus->msg_pos < bus->msg->len)
>> + aspeed_i2c_write(bus, ASPEED_I2CD_M_RX_CMD |
>> + ASPEED_I2CD_M_S_RX_CMD_LAST,
>> + ASPEED_I2C_CMD_REG);
>> + } else if (!(bus->msg->flags & I2C_M_RD) &&
>> + (irq_status & ASPEED_I2CD_INTR_TX_ACK)) {
>> + aspeed_i2c_write(bus, bus->msg->buf[bus->msg_pos++],
>> + ASPEED_I2C_BYTE_BUF_REG);
>> + aspeed_i2c_write(bus, ASPEED_I2CD_M_TX_CMD, ASPEED_I2C_CMD_REG);
>> + }
>
> is it safe to start a new transaction when in a interrupt handler ?
>
>> + /* Transmission complete: notify caller. */
>> + if (bus->msg_pos >= bus->msg->len)
>> + complete(&bus->cmd_complete);
>> +out:
>> + aspeed_i2c_write(bus, irq_status, ASPEED_I2C_INTR_STS_REG);
>
> so this is clearing the interrupt status just after having started
> a new transaction on the bus. It looks unsafe to me as it could
> clear the status of the just started transaction.
>
>> + spin_unlock(&bus->lock);
>> + return true;
>> +}
>> +
>> +static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
>> +{
>> + struct aspeed_i2c_bus *bus = dev_id;
>> +
>> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
>> + if (aspeed_i2c_slave_irq(bus)) {
>> + dev_dbg(bus->dev, "irq handled by slave.\n");
>> + return IRQ_HANDLED;
>> + }
>> +#endif
>> + if (aspeed_i2c_master_irq(bus)) {
>> + dev_dbg(bus->dev, "irq handled by master.\n");
>> + return IRQ_HANDLED;
>> + }
>> + dev_err(bus->dev, "irq not handled properly!\n");
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int aspeed_i2c_master_single_xfer(struct i2c_adapter *adap,
>> + struct i2c_msg *msg)
>> +{
>> + struct aspeed_i2c_bus *bus = adap->algo_data;
>> + unsigned long flags;
>> + u8 slave_addr;
>> + u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
>> + int ret = msg->len;
>> + unsigned long time_left;
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + bus->msg = msg;
>> + bus->msg_pos = 0;
>> + slave_addr = msg->addr << 1;
>> + if (msg->flags & I2C_M_RD) {
>> + slave_addr |= 1;
>> + command |= ASPEED_I2CD_M_RX_CMD;
>> + if (msg->len == 1)
>> + command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
>> + }
>> + aspeed_i2c_write(bus, slave_addr, ASPEED_I2C_BYTE_BUF_REG);
>> + aspeed_i2c_write(bus, command, ASPEED_I2C_CMD_REG);
>> + reinit_completion(&bus->cmd_complete);
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> +
>> + time_left = wait_for_completion_interruptible_timeout(
>> + &bus->cmd_complete, bus->adap.timeout * HZ * msg->len);
>
> Why do you multiply by * msg->len ?
>
>> + if (time_left == 0)
>> + return -ETIMEDOUT;
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + if (bus->cmd_err)
>> + ret = -EIO;
>> + bus->msg = NULL;
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> +
>> + return ret;
>> +}
>> +
>> +static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
>> + struct i2c_msg *msgs, int num)
>> +{
>> + struct aspeed_i2c_bus *bus = adap->algo_data;
>> + int ret;
>> + int i;
>> + unsigned long flags;
>> + unsigned long time_left;
>> +
>> + /* If bus is busy, attempt recovery. We assume a single master
>> + * environment.
>> + */
>> + if (aspeed_i2c_read(bus, ASPEED_I2C_CMD_REG) &
>> + ASPEED_I2CD_BUS_BUSY_STS) {
>> + ret = aspeed_i2c_recover_bus(bus);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + for (i = 0; i < num; i++) {
>> + ret = aspeed_i2c_master_single_xfer(adap, &msgs[i]);
>> + if (ret < 0)
>> + break;
>> + /* TODO: Support other forms of I2C protocol mangling. */
>> + if (msgs[i].flags & I2C_M_STOP) {
>> + spin_lock_irqsave(&bus->lock, flags);
>> + aspeed_i2c_write(bus, ASPEED_I2CD_M_STOP_CMD,
>> + ASPEED_I2C_CMD_REG);
>> + reinit_completion(&bus->cmd_complete);
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> +
>> + time_left = wait_for_completion_interruptible_timeout(
>> + &bus->cmd_complete,
>> + bus->adap.timeout * HZ);
>> + if (time_left == 0)
>> + return -ETIMEDOUT;
>> + }
>> + }
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + aspeed_i2c_write(bus, ASPEED_I2CD_M_STOP_CMD, ASPEED_I2C_CMD_REG);
>> + reinit_completion(&bus->cmd_complete);
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> +
>> + time_left = wait_for_completion_interruptible_timeout(
>> + &bus->cmd_complete, bus->adap.timeout * HZ);
>> + if (time_left == 0)
>> + return -ETIMEDOUT;
>> +
>> + /* If nothing went wrong, return number of messages transferred. */
>> + if (ret < 0)
>> + return ret;
>> + else
>> + return i;
>> +}
>> +
>> +static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
>> +{
>> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
>> +}
>> +
>> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
>> +static int aspeed_i2c_reg_slave(struct i2c_client *client)
>> +{
>> + struct aspeed_i2c_bus *bus;
>> + unsigned long flags;
>> + u32 addr_reg_val;
>> + u32 func_ctrl_reg_val;
>> +
>> + bus = client->adapter->algo_data;
>> + spin_lock_irqsave(&bus->lock, flags);
>> + if (bus->slave) {
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> + return -EINVAL;
>> + }
>> +
>> + /* Set slave addr. */
>> + addr_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_DEV_ADDR_REG);
>> + addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
>> + addr_reg_val |= client->addr & ASPEED_I2CD_DEV_ADDR_MASK;
>> + aspeed_i2c_write(bus, addr_reg_val, ASPEED_I2C_DEV_ADDR_REG);
>> +
>> + /* Switch from master mode to slave mode. */
>> + func_ctrl_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG);
>> + func_ctrl_reg_val &= ~ASPEED_I2CD_MASTER_EN;
>> + func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
>> + aspeed_i2c_write(bus, func_ctrl_reg_val, ASPEED_I2C_FUN_CTRL_REG);
>> +
>> + bus->slave = client;
>> + bus->slave_state = ASPEED_I2C_SLAVE_STOP;
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> + return 0;
>> +}
>> +
>> +static int aspeed_i2c_unreg_slave(struct i2c_client *client)
>> +{
>> + struct aspeed_i2c_bus *bus = client->adapter->algo_data;
>> + unsigned long flags;
>> + u32 func_ctrl_reg_val;
>> +
>> + spin_lock_irqsave(&bus->lock, flags);
>> + if (!bus->slave) {
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> + return -EINVAL;
>> + }
>> +
>> + /* Switch from slave mode to master mode. */
>> + func_ctrl_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG);
>> + func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
>> + func_ctrl_reg_val |= ASPEED_I2CD_MASTER_EN;
>> + aspeed_i2c_write(bus, func_ctrl_reg_val, ASPEED_I2C_FUN_CTRL_REG);
>> +
>> + bus->slave = NULL;
>> + spin_unlock_irqrestore(&bus->lock, flags);
>> + return 0;
>> +}
>> +#endif
>> +
>> +static const struct i2c_algorithm aspeed_i2c_algo = {
>> + .master_xfer = aspeed_i2c_master_xfer,
>> + .functionality = aspeed_i2c_functionality,
>> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
>> + .reg_slave = aspeed_i2c_reg_slave,
>> + .unreg_slave = aspeed_i2c_unreg_slave,
>> +#endif
>> +};
>> +
>> +static u32 aspeed_i2c_get_clk_reg_val(u32 divider_ratio)
>> +{
>> + unsigned int inc = 0, div;
>> + u32 scl_low, scl_high, data;
>> +
>> + for (div = 0; divider_ratio >= 16; div++) {
>> + inc |= (divider_ratio & 1);
>> + divider_ratio >>= 1;
>> + }
>> + divider_ratio += inc;
>> + scl_low = (divider_ratio >> 1) - 1;
>> + scl_high = divider_ratio - scl_low - 2;
>> + data = 0x77700300 | (scl_high << 16) | (scl_low << 12) | div;
>> + return data;
>> +}
>> +
>> +static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus,
>> + struct platform_device *pdev)
>> +{
>> + struct clk *pclk;
>> + u32 clk_freq;
>> + u32 divider_ratio;
>> + int ret;
>> +
>> + pclk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(pclk)) {
>> + dev_err(&pdev->dev, "clk_get failed\n");
>> + return PTR_ERR(pclk);
>> + }
>> + ret = of_property_read_u32(pdev->dev.of_node,
>> + "clock-frequency", &clk_freq);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev,
>> + "Could not read clock-frequency property\n");
>> + clk_freq = 100000;
>> + }
>> + divider_ratio = clk_get_rate(pclk) / clk_freq;
>> + /* We just need the clock rate, we don't actually use the clk object. */
>> + devm_clk_put(&pdev->dev, pclk);
>> +
>> + /* Set AC Timing */
>> + if (clk_freq / 1000 > 400) {
>> + aspeed_i2c_write(bus, aspeed_i2c_read(bus,
>> + ASPEED_I2C_FUN_CTRL_REG) |
>> + ASPEED_I2CD_M_HIGH_SPEED_EN |
>> + ASPEED_I2CD_M_SDA_DRIVE_1T_EN |
>> + ASPEED_I2CD_SDA_DRIVE_1T_EN,
>> + ASPEED_I2C_FUN_CTRL_REG);
>> +
>> + aspeed_i2c_write(bus, 0x3, ASPEED_I2C_AC_TIMING_REG2);
>> + aspeed_i2c_write(bus, aspeed_i2c_get_clk_reg_val(divider_ratio),
>> + ASPEED_I2C_AC_TIMING_REG1);
>> + } else {
>> + aspeed_i2c_write(bus, aspeed_i2c_get_clk_reg_val(divider_ratio),
>> + ASPEED_I2C_AC_TIMING_REG1);
>> + aspeed_i2c_write(bus, ASPEED_NO_TIMEOUT_CTRL,
>> + ASPEED_I2C_AC_TIMING_REG2);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void noop(struct irq_data *data) { }
>> +
>> +static struct irq_chip aspeed_i2c_irqchip = {
>> + .name = "ast-i2c",
>> + .irq_unmask = noop,
>> + .irq_mask = noop,
>> +};
>> +
>> +static int aspeed_i2c_probe_bus(struct platform_device *pdev)
>> +{
>> + struct aspeed_i2c_bus *bus;
>> + struct aspeed_i2c_controller *controller =
>> + dev_get_drvdata(pdev->dev.parent);
>> + struct resource *res;
>> + int ret, irq;
>> + u32 hwirq;
>> +
>> + bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
>> + if (!bus)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + bus->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(bus->base))
>> + return PTR_ERR(bus->base);
>> +
>> + bus->irq = platform_get_irq(pdev, 0);
>> + if (bus->irq < 0)
>> + return -ENXIO;
>> + ret = of_property_read_u32(pdev->dev.of_node, "interrupts", &hwirq);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "no I2C 'interrupts' property\n");
>> + return -ENXIO;
>> + }
>> + irq = irq_create_mapping(controller->irq_domain, hwirq);
>> + irq_set_chip_data(irq, controller);
>> + irq_set_chip_and_handler(irq, &aspeed_i2c_irqchip, handle_simple_irq);
>> + ret = devm_request_irq(&pdev->dev, bus->irq, aspeed_i2c_bus_irq,
>> + 0, dev_name(&pdev->dev), bus);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to request interrupt\n");
>> + return -ENXIO;
>> + }
>> +
>> + /* Initialize the I2C adapter */
>> + spin_lock_init(&bus->lock);
>> + init_completion(&bus->cmd_complete);
>> + bus->adap.owner = THIS_MODULE;
>> + bus->adap.retries = 0;
>> + bus->adap.timeout = 5;
>> + bus->adap.algo = &aspeed_i2c_algo;
>> + bus->adap.algo_data = bus;
>> + bus->adap.dev.parent = &pdev->dev;
>> + bus->adap.dev.of_node = pdev->dev.of_node;
>> + snprintf(bus->adap.name, sizeof(bus->adap.name), "Aspeed i2c");
>> +
>> + bus->dev = &pdev->dev;
>> +
>> + /* reset device: disable master & slave functions */
>> + aspeed_i2c_write(bus, 0, ASPEED_I2C_FUN_CTRL_REG);
>> +
>> + ret = aspeed_i2c_init_clk(bus, pdev);
>> + if (ret < 0)
>> + return ret;
>> +
>> + /* Enable Master Mode */
>> + aspeed_i2c_write(bus, aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG) |
>> + ASPEED_I2CD_MASTER_EN |
>> + ASPEED_I2CD_MULTI_MASTER_DIS, ASPEED_I2C_FUN_CTRL_REG);
>> +
>> + /* Set interrupt generation of I2C controller */
>> + aspeed_i2c_write(bus, ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
>> + ASPEED_I2CD_INTR_BUS_RECOVER_DONE |
>> + ASPEED_I2CD_INTR_SCL_TIMEOUT |
>> + ASPEED_I2CD_INTR_ABNORMAL |
>> + ASPEED_I2CD_INTR_NORMAL_STOP |
>> + ASPEED_I2CD_INTR_ARBIT_LOSS |
>> + ASPEED_I2CD_INTR_RX_DONE |
>> + ASPEED_I2CD_INTR_TX_NAK |
>> + ASPEED_I2CD_INTR_TX_ACK,
>> + ASPEED_I2C_INTR_CTRL_REG);
>> +
>> + ret = i2c_add_adapter(&bus->adap);
>> + if (ret < 0)
>> + return -ENXIO;
>> +
>> + platform_set_drvdata(pdev, bus);
>> +
>> + dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
>> + bus->adap.nr, bus->irq);
>> +
>> + return 0;
>> +}
>> +
>> +static int aspeed_i2c_remove_bus(struct platform_device *pdev)
>> +{
>> + struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
>> +
>> + i2c_del_adapter(&bus->adap);
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id aspeed_i2c_bus_of_table[] = {
>> + { .compatible = "aspeed,ast2400-i2c-bus", },
>> + { .compatible = "aspeed,ast2500-i2c-bus", },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
>> +
>> +static struct platform_driver aspeed_i2c_bus_driver = {
>> + .probe = aspeed_i2c_probe_bus,
>> + .remove = aspeed_i2c_remove_bus,
>> + .driver = {
>> + .name = "ast-i2c-bus",
>> + .of_match_table = aspeed_i2c_bus_of_table,
>> + },
>> +};
>> +
>> +static void aspeed_i2c_controller_irq(struct irq_desc *desc)
>> +{
>> + struct aspeed_i2c_controller *c = irq_desc_get_handler_data(desc);
>> + unsigned long p, status;
>> + unsigned int bus_irq;
>> +
>> + status = readl(c->base);
>> + for_each_set_bit(p, &status, ASPEED_I2C_NUM_BUS) {
>> + bus_irq = irq_find_mapping(c->irq_domain, p);
>> + generic_handle_irq(bus_irq);
>> + }
>> +}
>> +
>> +static int aspeed_i2c_probe_controller(struct platform_device *pdev)
>> +{
>> + struct aspeed_i2c_controller *controller;
>> + struct device_node *np;
>> + struct resource *res;
>> +
>> + controller = kzalloc(sizeof(*controller), GFP_KERNEL);
>
> use devm_kzalloc() may be ?
>
> C.
>
>> + if (!controller)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + controller->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(controller->base))
>> + return PTR_ERR(controller->base);
>> +
>> + controller->irq = platform_get_irq(pdev, 0);
>> + if (controller->irq < 0)
>> + return -ENXIO;
>> +
>> + controller->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
>> + ASPEED_I2C_NUM_BUS, &irq_domain_simple_ops, NULL);
>> + if (!controller->irq_domain)
>> + return -ENXIO;
>> + controller->irq_domain->name = "ast-i2c-domain";
>> +
>> + irq_set_chained_handler_and_data(controller->irq,
>> + aspeed_i2c_controller_irq, controller);
>> +
>> + controller->dev = &pdev->dev;
>> +
>> + platform_set_drvdata(pdev, controller);
>> +
>> + dev_info(controller->dev, "i2c controller registered, irq %d\n",
>> + controller->irq);
>> +
>> + for_each_child_of_node(pdev->dev.of_node, np) {
>> + of_platform_device_create(np, NULL, &pdev->dev);
>> + of_node_put(np);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int aspeed_i2c_remove_controller(struct platform_device *pdev)
>> +{
>> + struct aspeed_i2c_controller *controller = platform_get_drvdata(pdev);
>> +
>> + irq_domain_remove(controller->irq_domain);
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id aspeed_i2c_controller_of_table[] = {
>> + { .compatible = "aspeed,ast2400-i2c-controller", },
>> + { .compatible = "aspeed,ast2500-i2c-controller", },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(of, aspeed_i2c_controller_of_table);
>> +
>> +static struct platform_driver aspeed_i2c_controller_driver = {
>> + .probe = aspeed_i2c_probe_controller,
>> + .remove = aspeed_i2c_remove_controller,
>> + .driver = {
>> + .name = "ast-i2c-controller",
>> + .of_match_table = aspeed_i2c_controller_of_table,
>> + },
>> +};
>> +
>> +static int __init aspeed_i2c_driver_init(void)
>> +{
>> + int ret;
>> +
>> + ret = platform_driver_register(&aspeed_i2c_controller_driver);
>> + if (ret < 0)
>> + return ret;
>> + return platform_driver_register(&aspeed_i2c_bus_driver);
>> +}
>> +module_init(aspeed_i2c_driver_init);
>> +
>> +static void __exit aspeed_i2c_driver_exit(void)
>> +{
>> + platform_driver_unregister(&aspeed_i2c_bus_driver);
>> + platform_driver_unregister(&aspeed_i2c_controller_driver);
>> +}
>> +module_exit(aspeed_i2c_driver_exit);
>> +
>> +MODULE_AUTHOR("Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>");
>> +MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
>> +MODULE_LICENSE("GPL");
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-i2c" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply
* [PATCH] i2c: i2c-mux-gpio: update mux with gpiod_set_array_value_cansleep
From: Peter Rosin @ 2016-11-22 16:45 UTC (permalink / raw)
To: linux-kernel; +Cc: Peter Rosin, Peter Korsgaard, Wolfram Sang, linux-i2c
If the gpio controller supports it and the gpio lines are concentrated
to one gpio chip, the mux controller pins will get updated simultaneously.
Signed-off-by: Peter Rosin <peda@axentia.se>
---
drivers/i2c/muxes/i2c-mux-gpio.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
index 74a41b9228e3..bedbc88dbecb 100644
--- a/drivers/i2c/muxes/i2c-mux-gpio.c
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -23,15 +23,18 @@ struct gpiomux {
unsigned gpio_base;
struct mutex locked_lock;
int locked;
+ struct gpio_desc **gpios;
};
static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val)
{
+ int values[mux->data.n_gpios];
int i;
for (i = 0; i < mux->data.n_gpios; i++)
- gpio_set_value_cansleep(mux->gpio_base + mux->data.gpios[i],
- val & (1 << i));
+ values[i] = (val >> i) & 1;
+
+ gpiod_set_array_value_cansleep(mux->data.n_gpios, mux->gpios, values);
}
static int i2c_mux_gpio_select(struct i2c_mux_core *muxc, u32 chan)
@@ -241,12 +244,14 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev)
if (!parent)
return -EPROBE_DEFER;
- muxc = i2c_mux_alloc(parent, &pdev->dev, mux->data.n_values, 0, 0,
+ muxc = i2c_mux_alloc(parent, &pdev->dev, mux->data.n_values,
+ mux->data.n_values * sizeof(*mux->gpios), 0,
i2c_mux_gpio_select, NULL);
if (!muxc) {
ret = -ENOMEM;
goto alloc_failed;
}
+ mux->gpios = muxc->priv;
muxc->priv = mux;
platform_set_drvdata(pdev, muxc);
@@ -284,10 +289,12 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev)
goto err_request_gpio;
}
+ gpio_desc = gpio_to_desc(gpio_base + mux->data.gpios[i]);
+ mux->gpios[i] = gpio_desc;
+
if (!muxc->mux_locked)
continue;
- gpio_desc = gpio_to_desc(gpio_base + mux->data.gpios[i]);
gpio_dev = &gpio_desc->gdev->dev;
muxc->mux_locked = i2c_root_adapter(gpio_dev) == root;
}
--
2.1.4
^ permalink raw reply related
* Re: [PATCH v3 0/7] mux controller abstraction and iio/i2c muxes
From: Lars-Peter Clausen @ 2016-11-22 20:58 UTC (permalink / raw)
To: Peter Rosin, linux-kernel
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Jonathan Cameron,
Hartmut Knaack, Peter Meerwald-Stadler, Jonathan Corbet,
Arnd Bergmann, Greg Kroah-Hartman, linux-i2c, devicetree,
linux-iio, linux-doc
In-Reply-To: <1479734235-18837-1-git-send-email-peda@axentia.se>
On 11/21/2016 02:17 PM, Peter Rosin wrote:
[...]
> I have a piece of hardware that is using the same 3 GPIO pins
> to control four 8-way muxes. Three of them control ADC lines
> to an ADS1015 chip with an iio driver, and the last one
> controls the SDA line of an i2c bus. We have some deployed
> code to handle this, but you do not want to see it or ever
> hear about it. I'm not sure why I even mention it. Anyway,
> the situation has nagged me to no end for quite some time.
>
> So, after first getting more intimate with the i2c muxing code
> and later discovering the drivers/iio/inkern.c file and
> writing a couple of drivers making use of it, I came up with
> what I think is an acceptable solution; add a generic mux
> controller driver (and subsystem) that is shared between all
> instances, and combine that with an iio mux driver and a new
> generic i2c mux driver. The new i2c mux I called "simple"
> since it is only hooking the i2c muxing and the new mux
> controller (much like the alsa simple card driver does for ASoC).
While abstracting this properly is all nice and good and the way it should
be done, but it also adds a lot of complexity and the devicetree adds a lot
of restrictions on what can actually be represented.
There is a certain point where the fabric on a PCB becomes so complex that
it deserves to be a device on its own (like the audio fabric drivers).
Especially when the hardware is built with a certain application in mind and
the driver is supposed to impose policy which reflects this application. The
latter can often not properly be described with the primitives the
devicetree can offer.
And I think your setup is very borderline what can be done in a declarative
way only and it adds a lot of complexity over a more imperative solution in
form of a driver. I think it is worth investigating about having a driver
that is specific to your fabric and handles the interdependencies of the
discrete components.
^ permalink raw reply
* [PATCH V2] i2c: mux: pca954x: Add ACPI support for pca954x
From: tnhuynh @ 2016-11-23 8:52 UTC (permalink / raw)
To: Wolfram Sang, Peter Rosin, linux-i2c, linux-kernel
Cc: Loc Ho, Thang Nguyen, Phong Vo, patches, Tin Huynh
From: Tin Huynh <tnhuynh@apm.com>
This patch enables ACPI support for mux-pca954x driver.
Signed-off-by: Tin Huynh <tnhuynh@apm.com>
Change from v1 :
-Don't shadow id variable.
-Include sorted header.
-Redefine acpi_device_id.
-Add CONFIG_ACPI.
---
drivers/i2c/muxes/i2c-mux-pca954x.c | 29 ++++++++++++++++++++++++++++-
1 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index 1091346..1ad67cb 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -35,6 +35,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
@@ -120,6 +121,21 @@ struct pca954x {
};
MODULE_DEVICE_TABLE(i2c, pca954x_id);
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id pca954x_acpi_ids[] = {
+ { .id = "PCA9540", .driver_data = pca_9540 },
+ { .id = "PCA9542", .driver_data = pca_9540 },
+ { .id = "PCA9543", .driver_data = pca_9543 },
+ { .id = "PCA9544", .driver_data = pca_9544 },
+ { .id = "PCA9545", .driver_data = pca_9545 },
+ { .id = "PCA9546", .driver_data = pca_9545 },
+ { .id = "PCA9547", .driver_data = pca_9547 },
+ { .id = "PCA9548", .driver_data = pca_9548 },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, pca954x_acpi_ids);
+#endif
+
#ifdef CONFIG_OF
static const struct of_device_id pca954x_of_match[] = {
{ .compatible = "nxp,pca9540", .data = &chips[pca_9540] },
@@ -245,8 +261,18 @@ static int pca954x_probe(struct i2c_client *client,
match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
if (match)
data->chip = of_device_get_match_data(&client->dev);
- else
+ else if (id)
data->chip = &chips[id->driver_data];
+#ifdef CONFIG_ACPI
+ else {
+ const struct acpi_device_id *acpi_id;
+
+ acpi_id = acpi_match_device(pca954x_acpi_ids, &client->dev);
+ if (!acpi_id)
+ return -ENODEV;
+ data->chip = &chips[acpi_id->driver_data];
+ }
+#endif
data->last_chan = 0; /* force the first selection */
@@ -321,6 +347,7 @@ static int pca954x_resume(struct device *dev)
.name = "pca954x",
.pm = &pca954x_pm,
.of_match_table = of_match_ptr(pca954x_of_match),
+ .acpi_match_table = ACPI_PTR(pca954x_acpi_ids),
},
.probe = pca954x_probe,
.remove = pca954x_remove,
--
1.7.1
^ permalink raw reply related
* Re: [PATCH V2] i2c: mux: pca954x: Add ACPI support for pca954x
From: Peter Rosin @ 2016-11-23 9:08 UTC (permalink / raw)
To: tnhuynh, Wolfram Sang, linux-i2c, linux-kernel
Cc: Loc Ho, Thang Nguyen, Phong Vo, patches
In-Reply-To: <1479891177-23048-1-git-send-email-tnhuynh@apm.com>
On 2016-11-23 09:52, tnhuynh@apm.com wrote:
> From: Tin Huynh <tnhuynh@apm.com>
>
> This patch enables ACPI support for mux-pca954x driver.
>
> Signed-off-by: Tin Huynh <tnhuynh@apm.com>
>
> Change from v1 :
> -Don't shadow id variable.
> -Include sorted header.
> -Redefine acpi_device_id.
> -Add CONFIG_ACPI.
Please put these extra comment that do not belong in the changelog
below the following three dashes. Then git will ignore these comments
automatically, which simplifies applying the patch.
> ---
> drivers/i2c/muxes/i2c-mux-pca954x.c | 29 ++++++++++++++++++++++++++++-
> 1 files changed, 28 insertions(+), 1 deletions(-)
The customary position for extra comments is here, below the diffstat.
> diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
> index 1091346..1ad67cb 100644
> --- a/drivers/i2c/muxes/i2c-mux-pca954x.c
> +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
> @@ -35,6 +35,7 @@
> * warranty of any kind, whether express or implied.
> */
>
> +#include <linux/acpi.h>
> #include <linux/device.h>
> #include <linux/gpio/consumer.h>
> #include <linux/i2c.h>
> @@ -120,6 +121,21 @@ struct pca954x {
> };
> MODULE_DEVICE_TABLE(i2c, pca954x_id);
>
> +#ifdef CONFIG_ACPI
> +static const struct acpi_device_id pca954x_acpi_ids[] = {
> + { .id = "PCA9540", .driver_data = pca_9540 },
> + { .id = "PCA9542", .driver_data = pca_9540 },
> + { .id = "PCA9543", .driver_data = pca_9543 },
> + { .id = "PCA9544", .driver_data = pca_9544 },
> + { .id = "PCA9545", .driver_data = pca_9545 },
> + { .id = "PCA9546", .driver_data = pca_9545 },
> + { .id = "PCA9547", .driver_data = pca_9547 },
> + { .id = "PCA9548", .driver_data = pca_9548 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(acpi, pca954x_acpi_ids);
> +#endif
> +
> #ifdef CONFIG_OF
> static const struct of_device_id pca954x_of_match[] = {
> { .compatible = "nxp,pca9540", .data = &chips[pca_9540] },
> @@ -245,8 +261,18 @@ static int pca954x_probe(struct i2c_client *client,
> match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
> if (match)
> data->chip = of_device_get_match_data(&client->dev);
> - else
> + else if (id)
> data->chip = &chips[id->driver_data];
> +#ifdef CONFIG_ACPI
No, this #ifdef is not desired. If ACPI is not configured, acpi_match_device
will return NULL unconditionally and the compiler should compile the whole
else branch to be an unconditional "return -ENODEV;" and skip the dead code
at the end of the block. This is better than leaving data->chip as NULL and
oops later. It is also less cluttery to not have this extra #ifdef.
Cheers,
Peter
> + else {
> + const struct acpi_device_id *acpi_id;
> +
> + acpi_id = acpi_match_device(pca954x_acpi_ids, &client->dev);
> + if (!acpi_id)
> + return -ENODEV;
> + data->chip = &chips[acpi_id->driver_data];
> + }
> +#endif
>
> data->last_chan = 0; /* force the first selection */
>
> @@ -321,6 +347,7 @@ static int pca954x_resume(struct device *dev)
> .name = "pca954x",
> .pm = &pca954x_pm,
> .of_match_table = of_match_ptr(pca954x_of_match),
> + .acpi_match_table = ACPI_PTR(pca954x_acpi_ids),
> },
> .probe = pca954x_probe,
> .remove = pca954x_remove,
>
^ permalink raw reply
* Re: [PATCH v3 0/7] mux controller abstraction and iio/i2c muxes
From: Peter Rosin @ 2016-11-23 11:47 UTC (permalink / raw)
To: Lars-Peter Clausen, linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Jonathan Cameron,
Hartmut Knaack, Peter Meerwald-Stadler, Jonathan Corbet,
Arnd Bergmann, Greg Kroah-Hartman,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <b132143c-259b-6ed2-58c5-b223cc2e72df-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
On 2016-11-22 21:58, Lars-Peter Clausen wrote:
> On 11/21/2016 02:17 PM, Peter Rosin wrote:
> [...]
>> I have a piece of hardware that is using the same 3 GPIO pins
>> to control four 8-way muxes. Three of them control ADC lines
>> to an ADS1015 chip with an iio driver, and the last one
>> controls the SDA line of an i2c bus. We have some deployed
>> code to handle this, but you do not want to see it or ever
>> hear about it. I'm not sure why I even mention it. Anyway,
>> the situation has nagged me to no end for quite some time.
>>
>> So, after first getting more intimate with the i2c muxing code
>> and later discovering the drivers/iio/inkern.c file and
>> writing a couple of drivers making use of it, I came up with
>> what I think is an acceptable solution; add a generic mux
>> controller driver (and subsystem) that is shared between all
>> instances, and combine that with an iio mux driver and a new
>> generic i2c mux driver. The new i2c mux I called "simple"
>> since it is only hooking the i2c muxing and the new mux
>> controller (much like the alsa simple card driver does for ASoC).
>
> While abstracting this properly is all nice and good and the way it should
> be done, but it also adds a lot of complexity and the devicetree adds a lot
> of restrictions on what can actually be represented.
This is a characterization without any specifics. But is the
characterization true? You have two complaints, complexity
and restrictions with bindings.
> There is a certain point where the fabric on a PCB becomes so complex that
> it deserves to be a device on its own (like the audio fabric drivers).
> Especially when the hardware is built with a certain application in mind and
> the driver is supposed to impose policy which reflects this application. The
> latter can often not properly be described with the primitives the
> devicetree can offer.
>
> And I think your setup is very borderline what can be done in a declarative
> way only and it adds a lot of complexity over a more imperative solution in
> form of a driver. I think it is worth investigating about having a driver
> that is specific to your fabric and handles the interdependencies of the
> discrete components.
So, there are three "new" concepts:
1. Sticking a mux in front of an AD-converter. That's not all that
novel, nor complex. Quite the opposite, I'd say. In fact, I find it
a bit amazing that there is no in-kernel support for it.
2. Reusing the same GPIO-pins to drive different muxes. There are
obviously chips that work this way (as Jonathan pointed out) and
these will at some point get used in Linux devices. I guess they
already are used, but that people handle them in userspace. Or
something? If this is complex, which I question, it will still need
support at some point. At least that's what I believe.
3. Using the same GPIO pins to mux things handled by different
subsystems. Right, this is a bit crazy, and I'd rather not have this
requirement, but this HW is what it is so I'll need to handle it in
some way. It is also what stops me from falling back to a userspace
solution, which is probably connected to why #1 and #2 is not supported
by the kernel; everybody probably does muxing in userspace. Which is
not necessarily a good idea, nor how it's supposed to be done...
So, the only thing that's out of the ordinary (as I see it), is #3.
The question that then needs an answer is how the in-kernel solution
for #1 and #2 would look if we do not consider #3.
And I claim that the desired solution to #1 and #2 is pretty close
to my proposal.
A. You do not want mux-controller drivers in every subsystem that
needs them.
B. You do not want every mux-consumer to know the specifics of how to
operate every kind of mux; there are muxes that are not controlled
with GPIO pins...
C. When you implement muxing in a subsystem, there will in some cases
be a need to handle parallel muxing, where there is a need to share
mux-controllers.
It just feels right to separate out the mux-controller and refer to
it from where a mux is needed. It solves #1 and #2. And, of course,
as a bonus #3 is also solved. But my bias is obvious.
And that leads us to the restrictions with the bindings. And the same
thing happens; the solution for #2 also solves #3.
So how do you refer to a mux-controller from where it's needed? My
first proposal used a dt phandle, for the second round I put them in
the parent node. It would be super if it was possible for the mux-
consumer to create the mux-controller device from the same dt
node that is already bound to the mux-consumer. The problem is that
the mux-consumer should not hard-code which mux-controller device it
should create. The best I can think of is some kind of 'mux-compatible'
attribute, that works like the standard 'compatible' attribute. That
would simplify the bindings for the normal case (#1) where the mux-
controller isn't shared (#2 and #3). Maybe it's possible to fix this
issue somehow? I simply don't know?
Cheers,
Peter
--
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^ permalink raw reply
* [PATCH v2] i2c: i2c-mux-gpio: update mux with gpiod_set_array_value_cansleep
From: Peter Rosin @ 2016-11-23 13:33 UTC (permalink / raw)
To: linux-kernel; +Cc: Peter Rosin, Peter Korsgaard, Wolfram Sang, linux-i2c
If the gpio controller supports it and the gpio lines are concentrated
to one gpio chip, the mux controller pins will get updated simultaneously.
Signed-off-by: Peter Rosin <peda@axentia.se>
---
drivers/i2c/muxes/i2c-mux-gpio.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
Sorry about any confusion with v1, it had another unrelated patch
underneath that made it hard to apply it. I had forgot about that
one...
Anyway, this version should be better. Sorry again.
Cheers,
Peter
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
index e5cf26eefa97..62d033a7adf2 100644
--- a/drivers/i2c/muxes/i2c-mux-gpio.c
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -21,15 +21,18 @@
struct gpiomux {
struct i2c_mux_gpio_platform_data data;
unsigned gpio_base;
+ struct gpio_desc **gpios;
};
static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val)
{
+ int values[mux->data.n_gpios];
int i;
for (i = 0; i < mux->data.n_gpios; i++)
- gpio_set_value_cansleep(mux->gpio_base + mux->data.gpios[i],
- val & (1 << i));
+ values[i] = (val >> i) & 1;
+
+ gpiod_set_array_value_cansleep(mux->data.n_gpios, mux->gpios, values);
}
static int i2c_mux_gpio_select(struct i2c_mux_core *muxc, u32 chan)
@@ -176,12 +179,14 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev)
if (!parent)
return -EPROBE_DEFER;
- muxc = i2c_mux_alloc(parent, &pdev->dev, mux->data.n_values, 0, 0,
+ muxc = i2c_mux_alloc(parent, &pdev->dev, mux->data.n_values,
+ mux->data.n_values * sizeof(*mux->gpios), 0,
i2c_mux_gpio_select, NULL);
if (!muxc) {
ret = -ENOMEM;
goto alloc_failed;
}
+ mux->gpios = muxc->priv;
muxc->priv = mux;
platform_set_drvdata(pdev, muxc);
@@ -219,10 +224,12 @@ static int i2c_mux_gpio_probe(struct platform_device *pdev)
goto err_request_gpio;
}
+ gpio_desc = gpio_to_desc(gpio_base + mux->data.gpios[i]);
+ mux->gpios[i] = gpio_desc;
+
if (!muxc->mux_locked)
continue;
- gpio_desc = gpio_to_desc(gpio_base + mux->data.gpios[i]);
gpio_dev = &gpio_desc->gdev->dev;
muxc->mux_locked = i2c_root_adapter(gpio_dev) == root;
}
--
2.1.4
^ permalink raw reply related
* Re: [PATCH 1/2] i2c: designware: report short transfers
From: Jarkko Nikula @ 2016-11-23 14:13 UTC (permalink / raw)
To: Mika Westerberg, Russell King
Cc: Andrew Jackson, Liviu Dudau, Wolfram Sang, Andy Shevchenko,
linux-i2c, linux-arm-kernel
In-Reply-To: <20161121103200.GG1446@lahna.fi.intel.com>
On 21.11.2016 12:32, Mika Westerberg wrote:
> On Fri, Nov 18, 2016 at 07:40:04PM +0000, Russell King wrote:
>> Rather than reporting success for a short transfer due to interrupt
>> latency, report an error both to the caller, as well as to the kernel
>> log.
>>
>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>
> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
^ permalink raw reply
* Re: [PATCH 2/2] i2c: designware: fix rx fifo depth tracking
From: Jarkko Nikula @ 2016-11-23 14:13 UTC (permalink / raw)
To: Mika Westerberg, Russell King
Cc: Andrew Jackson, Liviu Dudau, Wolfram Sang, Andy Shevchenko,
linux-i2c, linux-arm-kernel
In-Reply-To: <20161121104032.GH1446@lahna.fi.intel.com>
On 21.11.2016 12:40, Mika Westerberg wrote:
> On Fri, Nov 18, 2016 at 07:40:10PM +0000, Russell King wrote:
>> When loading the TX fifo to receive bytes on the I2C bus, we incorrectly
>> count the number of bytes:
>>
>> rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
>>
>> while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
>> if (rx_limit - dev->rx_outstanding <= 0)
>> break;
>> rx_limit--;
>> dev->rx_outstanding++;
>> }
>>
>> DW_IC_RXFLR indicates how many bytes are available to be read in the
>> FIFO, dev->rx_fifo_depth is the FIFO size, and dev->rx_outstanding is
>> the number of bytes that we've requested to be read so far, but which
>> have not been read.
>>
>> Firstly, increasing dev->rx_outstanding and decreasing rx_limit and then
>> comparing them results in each byte consuming "two" bytes in this
>> tracking, so this is obviously wrong.
>>
>> Secondly, the number of bytes that _could_ be received into the FIFO at
>> any time is the number of bytes we have so far requested but not yet
>> read from the FIFO - in other words dev->rx_outstanding.
>>
>> So, in order to request enough bytes to fill the RX FIFO, we need to
>> request dev->rx_fifo_depth - dev->rx_outstanding bytes.
>>
>> Modifying the code thusly results in us reaching the maximum number of
>> bytes outstanding each time we queue more "receive" operations, provided
>> the transfer allows that to happen.
>>
>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>
> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
^ permalink raw reply
* Re: [PATCH 1/1] i2c: designware: Consolidate default functionality bits
From: Jarkko Nikula @ 2016-11-23 14:16 UTC (permalink / raw)
To: Alexander Stein, Andy Shevchenko, Mika Westerberg, Wolfram Sang; +Cc: linux-i2c
In-Reply-To: <1479725000-22513-1-git-send-email-alexander.stein@systec-electronic.com>
On 21.11.2016 12:43, Alexander Stein wrote:
> Use a common place for default functionality bits for both platform
> and pci driver.
>
> Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
> ---
> This patch requires commit c3ae106050b9 ("i2c: designware: Implement support
> for SMBus block read and write") which is included in current i2c/for-next
> branch.
> BTW: Do merrifield and medfield actually not support 10bit addressing?
>
Andy, do you know?
> drivers/i2c/busses/i2c-designware-core.h | 8 ++++++++
> drivers/i2c/busses/i2c-designware-pcidrv.c | 9 +--------
> drivers/i2c/busses/i2c-designware-platdrv.c | 9 +--------
> 3 files changed, 10 insertions(+), 16 deletions(-)
>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
^ permalink raw reply
* Re: [PATCH v3 3/5] i2c: designware: Add slave definitions
From: Luis Oliveira @ 2016-11-23 14:36 UTC (permalink / raw)
To: Rob Herring, Andy Shevchenko
Cc: Luis Oliveira, wsa, mark.rutland, jarkko.nikula, mika.westerberg,
linux-i2c, devicetree, linux-kernel, Ramiro.Oliveira, Joao.Pinto,
CARLOS.PALMINHA
In-Reply-To: <20161118170155.chrdpguohgl6vo5f@rob-hp-laptop>
OK, I will create a "mode" string property in the devicetree that can be
"master" or "slave".
Thank you all,
Luis
On 18-Nov-16 17:01, Rob Herring wrote:
> On Fri, Nov 18, 2016 at 02:35:52PM +0200, Andy Shevchenko wrote:
>> On Fri, 2016-11-18 at 11:19 +0000, Luis Oliveira wrote:
>>> - Add slave defintitions to i2c-designware-core
>>> - Changes in Kconfig to auto-enable I2C_SLAVE when compiling the
>>> modules
>>> - Add compatible string to designware-core.txt explaining the
>>> devicetree bindings
>>>
>>
>>> --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
>>> +++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
>>> @@ -2,7 +2,9 @@
>>>
>>> Required properties :
>>>
>>> - - compatible : should be "snps,designware-i2c"
>>> + - compatible : should be:
>>> + - "snps,designware-i2c" to setup the hardware block as I2C master.
>>> + - "snps,designware-i2c-slave" to setup the hardware block as I2C
>>> slave.
>> Not sure about this one.
>>
>> Compatible string is more generic than list of modes. Basically you have
>> to add a property which selects mode.
> Yes, agreed. And come up with a common property.
>
>> DT people's ACK is a must for this change.
>>
>>
>> --- a/drivers/i2c/busses/Kconfig
>>> +++ b/drivers/i2c/busses/Kconfig
>>> @@ -470,6 +470,7 @@ config I2C_DESIGNWARE_CORE
>>> config I2C_DESIGNWARE_PLATFORM
>>> tristate "Synopsys DesignWare Platform"
>>> select I2C_DESIGNWARE_CORE
>>> + select I2C_SLAVE
>>>
>> Common rule, generic dependencies usually go first
>>
>> select I2C_SLAVE
>> select I2C_DESIGNWARE_CORE
>>
>> --
>> Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> Intel Finland Oy
--
Best regards,
Luis
^ permalink raw reply
* Re: [PATCH 1/1] i2c: designware: Consolidate default functionality bits
From: Andy Shevchenko @ 2016-11-23 16:12 UTC (permalink / raw)
To: Jarkko Nikula, Alexander Stein, Mika Westerberg, Wolfram Sang; +Cc: linux-i2c
In-Reply-To: <67a95b37-73e3-7105-d9d1-7bc60c8b6fcc@linux.intel.com>
On Wed, 2016-11-23 at 16:16 +0200, Jarkko Nikula wrote:
> On 21.11.2016 12:43, Alexander Stein wrote:
> > Use a common place for default functionality bits for both platform
> > and pci driver.
> >
> > Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.co
> > m>
> > ---
> > This patch requires commit c3ae106050b9 ("i2c: designware: Implement
> > support
> > for SMBus block read and write") which is included in current
> > i2c/for-next
> > branch.
> > BTW: Do merrifield and medfield actually not support 10bit
> > addressing?
> >
>
> Andy, do you know?
Merrifield TRM: "Both 7-bit and 10-bit addressing modes are supported."
Same in Medfield TRM.
So, feel free to use this reference to apply a corresponding change. I
will Ack it.
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply
* Re: [PATCH v4 1/2] i2c: aspeed: added driver for Aspeed I2C
From: Brendan Higgins @ 2016-11-23 23:52 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Wolfram Sang, robh+dt, mark.rutland, devicetree, OpenBMC Maillist,
linux-i2c
In-Reply-To: <28078e6d-f5e4-da59-e226-baa9a60a4b19@kaod.org>
> is it safe to start a new transaction when in a interrupt handler ?
Yep, i2c_transfer and most of the other functions in the i2c API that
wrap the implementations already lock for you.
> Why do you multiply by * msg->len ?
I thought it might make sense to make timeout proportional to message
length, so their would be a timeout per byte, like what the hardware
already does. I guess we should just leave that up to the user to
determine on their own?
> use devm_kzalloc() may be ?
Whoops, good catch. Will update in next version.
^ permalink raw reply
* Re: [PATCH v4 1/2] i2c: aspeed: added driver for Aspeed I2C
From: Brendan Higgins @ 2016-11-24 0:45 UTC (permalink / raw)
To: Kachalov Anton
Cc: Cédric Le Goater, wsa@the-dreams.de, robh+dt@kernel.org,
mark.rutland@arm.com, devicetree@vger.kernel.org,
openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org
In-Reply-To: <584151479839034@web17g.yandex.ru>
> I would like to add my five cents here. Do not limit the bus_clk with 400kHz (FM) while HighSpeed is above
> 1MHz (above FM+ devices). I've successfully tested FM+ (1Mhz) in a quite big i2c network (a number of
> pca9600, pca9675, pca9848) with at least eight AST2150 SoCs on the common bus.
Interesting point, on one hand I would argue that we should force
people to use either FM or FM+ in a conformant manner. But on the
other hand, I suppose a device may not support FM+'s electrical
characteristics, but could run at a higher clock rate, and it is
better to allow that than forcing FM+. Maybe I should remove any kind
of restriction, and just allow the clock to be set to any conformant
frequency and expose FM+ as a separate option in device tree.
Thoughts?
> BTW. Just a lame question. If the device isn't designed to work on the higher speed (like standard of FM)
> while the bus selected as FM+, would those kind of devices just unoperate or may have undefined behavior
> and disturb the SDA/SCL? Just wondering to dynamically slowdown down to 100Khz (if needed) for the
> specific slave, but keep high rate (FM+) at the normal operation.
I have never tried this myself, but I suspect there may be other
issues with running an FM device on an FM+ bus: FM+ uses a higher
current to make the rise times on the line faster. A bigger problem:
if a master wanted to select a high speed capable slave, it could
write the address at a high speed which might look like a different
address to a low speed slave that is incapable of sampling the address
properly. So I do not think that supporting dynamically slowing down
an I2C bus makes much sense. An interesting idea, though.
^ permalink raw reply
* i2c /i801_smbus bug/issue
From: Piotr Kasprzak @ 2016-11-21 11:59 UTC (permalink / raw)
To: wsa, kean.ho.chew, james.d.ralston, seth.heasley
[-- Attachment #1: Type: text/plain, Size: 612 bytes --]
Hi
i dont know who is responsible for driver for i2c intel, and where to raport bug
on my board Apollo Lake - Asrock J3455-ITX im getting on latets kernel master 4.9rc5 following issue
[ 2.079564] i2c /dev entries driver
[ 2.079911] i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A
[ 2.079913] i801_smbus 0000:00:1f.1: PCI INT A: not connected
[ 2.079939] i801_smbus 0000:00:1f.1: SPD Write Disable is set
[ 2.079964] i801_smbus 0000:00:1f.1: Failed to allocate irq -2147483648: -107
[ 2.079973] i801_smbus 0000:00:1f.1: SMBus using polling
here my hardware log
[-- Attachment #2: 03_Hardware.log --]
[-- Type: application/octet-stream, Size: 52038 bytes --]
################################################################################
# ... output of lspci -vvvvnn
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
00:00.0 Host bridge [0600]: Intel Corporation Device [8086:5af0] (rev 0b)
Subsystem: ASRock Incorporation Device [1849:5af0]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:5a85] (rev 0b) (prog-if 00 [VGA controller])
Subsystem: ASRock Incorporation Device [1849:5a85]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 124
Region 0: Memory at 90000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at 80000000 (64-bit, prefetchable) [size=256M]
Region 4: I/O ports at f000 [size=64]
[virtual] Expansion ROM at 000c0000 [disabled] [size=128K]
Capabilities: [40] Vendor Specific Information: Len=0c <?>
Capabilities: [70] Express (v2) Root Complex Integrated Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
Capabilities: [ac] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0f00c Data: 41e1
Capabilities: [d0] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Process Address Space ID (PASID)
PASIDCap: Exec+ Priv-, Max PASID Width: 14
PASIDCtl: Enable- Exec- Priv-
Capabilities: [200 v1] Address Translation Service (ATS)
ATSCap: Invalidate Queue Depth: 00
ATSCtl: Enable-, Smallest Translation Unit: 00
Capabilities: [300 v1] Page Request Interface (PRI)
PRICtl: Enable- Reset-
PRISta: RF- UPRGI- Stopped-
Page Request Capacity: 00008000, Page Request Allocation: 00000000
Kernel driver in use: i915
00:0e.0 Audio device [0403]: Intel Corporation Device [8086:5a98] (rev 0b)
Subsystem: ASRock Incorporation Device [1849:c892]
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 127
Region 0: Memory at 91310000 (64-bit, non-prefetchable) [size=16K]
Region 4: Memory at 91000000 (64-bit, non-prefetchable) [size=1M]
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Vendor Specific Information: Len=14 <?>
Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee0f00c Data: 4182
Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0
ExtTag- RBE-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
Kernel driver in use: snd_hda_intel
Kernel modules: snd_soc_skl, snd_hda_intel
00:0f.0 Communication controller [0780]: Intel Corporation Device [8086:5a9a] (rev 0b)
Subsystem: ASRock Incorporation Device [1849:5a9a]
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 255
Region 0: Memory at 9131b000 (64-bit, non-prefetchable) [size=4K]
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [8c] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [a4] Vendor Specific Information: Len=14 <?>
00:12.0 SATA controller [0106]: Intel Corporation Device [8086:5ae3] (rev 0b) (prog-if 01 [AHCI 1.0])
Subsystem: ASRock Incorporation Device [1849:5ae3]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 19
Region 0: Memory at 91314000 (32-bit, non-prefetchable) [size=8K]
Region 1: Memory at 91318000 (32-bit, non-prefetchable) [size=256]
Region 2: I/O ports at f090 [size=8]
Region 3: I/O ports at f080 [size=4]
Region 4: I/O ports at f060 [size=32]
Region 5: Memory at 91317000 (32-bit, non-prefetchable) [size=2K]
Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit-
Address: 00000000 Data: 0000
Capabilities: [70] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst+ PME-Enable+ DSel=0 DScale=0 PME-
Capabilities: [a8] SATA HBA v1.0 BAR4 Offset=00000004
Kernel driver in use: ahci
00:13.0 PCI bridge [0604]: Intel Corporation Device [8086:5ad8] (rev fb) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 120
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: 91200000-912fffff
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 256 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #3, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s <1us, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #2, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0f00c Data: 4161
Capabilities: [90] Subsystem: ASRock Incorporation Device [1849:5ad8]
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v0] #00
Capabilities: [140 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [150 v0] #00
Capabilities: [200 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
Kernel driver in use: pcieport
00:13.1 PCI bridge [0604]: Intel Corporation Device [8086:5ad9] (rev fb) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin B routed to IRQ 121
Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
I/O behind bridge: 0000f000-00000fff
Memory behind bridge: fff00000-000fffff
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 256 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #4, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s <1us, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train+ SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #3, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
Changed: MRL- PresDet- LinkState-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0f00c Data: 4181
Capabilities: [90] Subsystem: ASRock Incorporation Device [1849:5ad9]
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
Capabilities: [100 v0] #00
Capabilities: [140 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [150 v0] #00
Capabilities: [200 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
Kernel driver in use: pcieport
00:13.2 PCI bridge [0604]: Intel Corporation Device [8086:5ada] (rev fb) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin C routed to IRQ 122
Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
I/O behind bridge: 0000d000-0000dfff
Memory behind bridge: 91100000-911fffff
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 256 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #5, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s <1us, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #4, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0f00c Data: 41a1
Capabilities: [90] Subsystem: ASRock Incorporation Device [1849:5ada]
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v0] #00
Capabilities: [140 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [150 v0] #00
Capabilities: [200 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
Kernel driver in use: pcieport
00:13.3 PCI bridge [0604]: Intel Corporation Device [8086:5adb] (rev fb) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin D routed to IRQ 123
Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
I/O behind bridge: 0000f000-00000fff
Memory behind bridge: fff00000-000fffff
Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0
ExtTag- RBE+
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 256 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #6, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s <1us, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train+ SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #5, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
Changed: MRL- PresDet- LinkState-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0f00c Data: 41c1
Capabilities: [90] Subsystem: ASRock Incorporation Device [1849:5adb]
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
Capabilities: [100 v0] #00
Capabilities: [140 v1] Access Control Services
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [150 v0] #00
Capabilities: [200 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
Kernel driver in use: pcieport
00:15.0 USB controller [0c03]: Intel Corporation Device [8086:5aa8] (rev 0b) (prog-if 30 [XHCI])
Subsystem: ASRock Incorporation Device [1849:5aa8]
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 126
Region 0: Memory at 91300000 (64-bit, non-prefetchable) [size=64K]
Capabilities: [70] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] MSI: Enable+ Count=1/8 Maskable- 64bit+
Address: 00000000fee0f00c Data: 4152
Capabilities: [90] Vendor Specific Information: Len=14 <?>
Kernel driver in use: xhci_hcd
00:1f.0 ISA bridge [0601]: Intel Corporation Device [8086:5ae8] (rev 0b)
Subsystem: ASRock Incorporation Device [1849:5ae8]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
00:1f.1 SMBus [0c05]: Intel Corporation Broxton SMBus Controller [8086:5ad4] (rev 0b)
Subsystem: ASRock Incorporation Broxton SMBus Controller [1849:5ad4]
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ -2147483648
Region 0: Memory at 91316000 (64-bit, non-prefetchable) [size=256]
Region 4: I/O ports at f040 [size=32]
Kernel driver in use: i801_smbus
01:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 11)
Subsystem: ASRock Incorporation RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (Motherboard (one of many)) [1849:8168]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 125
Region 0: I/O ports at e000 [size=256]
Region 2: Memory at 91204000 (64-bit, non-prefetchable) [size=4K]
Region 4: Memory at 91200000 (64-bit, prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Address: 00000000fee0f00c Data: 4122
Capabilities: [70] Express (v2) Endpoint, MSI 01
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 10.000W
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Via message/WAKE#
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [b0] MSI-X: Enable- Count=4 Masked-
Vector table: BAR=4 offset=00000000
PBA: BAR=4 offset=00000800
Capabilities: [d0] Vital Product Data
Not readable
Capabilities: [100 v1] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Capabilities: [140 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status: NegoPending- InProgress-
Capabilities: [160 v1] Device Serial Number 01-00-00-00-68-4c-e0-00
Capabilities: [170 v1] Latency Tolerance Reporting
Max snoop latency: 3145728ns
Max no snoop latency: 3145728ns
Kernel driver in use: r8169
03:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0])
Subsystem: ASRock Incorporation ASM1062 Serial ATA Controller (Motherboard) [1849:0612]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 20
Region 0: I/O ports at d050 [size=8]
Region 1: I/O ports at d040 [size=4]
Region 2: I/O ports at d030 [size=8]
Region 3: I/O ports at d020 [size=4]
Region 4: I/O ports at d000 [size=32]
Region 5: Memory at 91100000 (32-bit, non-prefetchable) [size=512]
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
Address: 00000000 Data: 0000
Capabilities: [78] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s unlimited, L1 <2us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR-, OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed- WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
Status: NegoPending- InProgress-
Kernel driver in use: ahci
################################################################################
# ... output of lsusb -vvv
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 3.00
bDeviceClass 9 Hub
bDeviceSubClass 0
bDeviceProtocol 3
bMaxPacketSize0 9
idVendor 0x1d6b Linux Foundation
idProduct 0x0003 3.0 root hub
bcdDevice 4.09
iManufacturer 3 Linux 4.9.0-rc5+ xhci-hcd
iProduct 2 xHCI Host Controller
iSerial 1 0000:00:15.0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 31
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xe0
Self Powered
Remote Wakeup
MaxPower 0mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 9 Hub
bInterfaceSubClass 0
bInterfaceProtocol 0 Full speed (or root) hub
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0004 1x 4 bytes
bInterval 12
bMaxBurst 0
Hub Descriptor:
bLength 12
bDescriptorType 42
nNbrPorts 7
wHubCharacteristic 0x000a
No power switching (usb 1.0)
Per-port overcurrent protection
bPwrOn2PwrGood 10 * 2 milli seconds
bHubContrCurrent 0 milli Ampere
bHubDecLat 0.0 micro seconds
wHubDelay 0 nano seconds
DeviceRemovable 0x00
Hub Port Status:
Port 1: 0000.02a0 5Gbps power Rx.Detect
Port 2: 0000.02a0 5Gbps power Rx.Detect
Port 3: 0000.02a0 5Gbps power Rx.Detect
Port 4: 0000.02a0 5Gbps power Rx.Detect
Port 5: 0000.02a0 5Gbps power Rx.Detect
Port 6: 0000.02a0 5Gbps power Rx.Detect
Port 7: 0000.02a0 5Gbps power Rx.Detect
Binary Object Store Descriptor:
bLength 5
bDescriptorType 15
wTotalLength 15
bNumDeviceCaps 1
SuperSpeed USB Device Capability:
bLength 10
bDescriptorType 16
bDevCapabilityType 3
bmAttributes 0x02
Latency Tolerance Messages (LTM) Supported
wSpeedsSupported 0x0008
Device can operate at SuperSpeed (5Gbps)
bFunctionalitySupport 3
Lowest fully-functional device speed is SuperSpeed (5Gbps)
bU1DevExitLat 10 micro seconds
bU2DevExitLat 512 micro seconds
Device Status: 0x0001
Self Powered
Bus 001 Device 004: ID 045e:0745 Microsoft Corp. Nano Transceiver v1.0 for Bluetooth
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x045e Microsoft Corp.
idProduct 0x0745 Nano Transceiver v1.0 for Bluetooth
bcdDevice 6.34
iManufacturer 1 Microsoft
iProduct 2 Microsoft? Nano Transceiver v2.0
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 84
bNumInterfaces 3
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xa0
(Bus Powered)
Remote Wakeup
MaxPower 100mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 1 Boot Interface Subclass
bInterfaceProtocol 1 Keyboard
iInterface 0
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.11
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 57
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0008 1x 8 bytes
bInterval 4
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 1
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 1 Boot Interface Subclass
bInterfaceProtocol 2 Mouse
iInterface 0
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.11
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 295
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82 EP 2 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x000a 1x 10 bytes
bInterval 1
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 2
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 0
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.11
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 319
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x83 EP 3 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0020 1x 32 bytes
bInterval 1
Device Status: 0x0000
(Bus Powered)
Bus 001 Device 003: ID 413c:2003 Dell Computer Corp. Keyboard
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 1.10
bDeviceClass 0
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 8
idVendor 0x413c Dell Computer Corp.
idProduct 0x2003 Keyboard
bcdDevice 3.01
iManufacturer 1 Dell
iProduct 2 Dell USB Keyboard
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 34
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xa0
(Bus Powered)
Remote Wakeup
MaxPower 70mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 1 Boot Interface Subclass
bInterfaceProtocol 1 Keyboard
iInterface 0
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.10
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 65
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0008 1x 8 bytes
bInterval 24
Device Status: 0x0000
(Bus Powered)
Bus 001 Device 002: ID 0471:2168 Philips (or NXP)
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 1.10
bDeviceClass 0
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 8
idVendor 0x0471 Philips (or NXP)
idProduct 0x2168
bcdDevice 1.04
iManufacturer 1 PHILIPS
iProduct 2 OVU710023
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 34
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xa0
(Bus Powered)
Remote Wakeup
MaxPower 100mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 1 Boot Interface Subclass
bInterfaceProtocol 1 Keyboard
iInterface 0
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.11
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 479
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0008 1x 8 bytes
bInterval 10
Device Status: 0x0000
(Bus Powered)
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 9 Hub
bDeviceSubClass 0
bDeviceProtocol 1 Single TT
bMaxPacketSize0 64
idVendor 0x1d6b Linux Foundation
idProduct 0x0002 2.0 root hub
bcdDevice 4.09
iManufacturer 3 Linux 4.9.0-rc5+ xhci-hcd
iProduct 2 xHCI Host Controller
iSerial 1 0000:00:15.0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 25
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xe0
Self Powered
Remote Wakeup
MaxPower 0mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 9 Hub
bInterfaceSubClass 0
bInterfaceProtocol 0 Full speed (or root) hub
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0004 1x 4 bytes
bInterval 12
Hub Descriptor:
bLength 11
bDescriptorType 41
nNbrPorts 8
wHubCharacteristic 0x000a
No power switching (usb 1.0)
Per-port overcurrent protection
TT think time 8 FS bits
bPwrOn2PwrGood 10 * 2 milli seconds
bHubContrCurrent 0 milli Ampere
DeviceRemovable 0x00 0x00
PortPwrCtrlMask 0xff 0xff
Hub Port Status:
Port 1: 0000.0100 power
Port 2: 0000.0100 power
Port 3: 0000.0303 lowspeed power enable connect
Port 4: 0000.0303 lowspeed power enable connect
Port 5: 0000.0100 power
Port 6: 0000.0103 power enable connect
Port 7: 0000.0100 power
Port 8: 0000.0100 power
Device Status: 0x0003
Self Powered
Remote Wakeup Enabled
################################################################################
# ... output of lsusb -t
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/7p, 5000M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/8p, 480M
|__ Port 3: Dev 2, If 0, Class=Human Interface Device, Driver=usbhid, 1.5M
|__ Port 4: Dev 3, If 0, Class=Human Interface Device, Driver=usbhid, 1.5M
|__ Port 6: Dev 4, If 2, Class=Human Interface Device, Driver=usbhid, 12M
|__ Port 6: Dev 4, If 0, Class=Human Interface Device, Driver=usbhid, 12M
|__ Port 6: Dev 4, If 1, Class=Human Interface Device, Driver=usbhid, 12M
################################################################################
# ... output of cat /proc/cpuinfo
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 92
model name : Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
stepping : 9
microcode : 0x1c
cpu MHz : 2199.920
cache size : 1024 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 21
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust smep erms mpx rdseed smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts
bugs : monitor
bogomips : 2996.00
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 92
model name : Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
stepping : 9
microcode : 0x1c
cpu MHz : 2199.920
cache size : 1024 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 4
apicid : 2
initial apicid : 2
fpu : yes
fpu_exception : yes
cpuid level : 21
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust smep erms mpx rdseed smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts
bugs : monitor
bogomips : 2999.27
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 92
model name : Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
stepping : 9
microcode : 0x1c
cpu MHz : 2199.920
cache size : 1024 KB
physical id : 0
siblings : 4
core id : 2
cpu cores : 4
apicid : 4
initial apicid : 4
fpu : yes
fpu_exception : yes
cpuid level : 21
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust smep erms mpx rdseed smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts
bugs : monitor
bogomips : 3000.79
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 92
model name : Intel(R) Celeron(R) CPU J3455 @ 1.50GHz
stepping : 9
microcode : 0x1c
cpu MHz : 2199.920
cache size : 1024 KB
physical id : 0
siblings : 4
core id : 3
cpu cores : 4
apicid : 6
initial apicid : 6
fpu : yes
fpu_exception : yes
cpuid level : 21
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg cx16 xtpr pdcm sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave rdrand lahf_lm 3dnowprefetch intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust smep erms mpx rdseed smap clflushopt sha_ni xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts
bugs : monitor
bogomips : 3000.70
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
power management:
################################################################################
# ... output of get_governor_details
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
/sys/devices/system/cpu
cpu0 : <dir>
cpu1 : <dir>
cpu2 : <dir>
cpu3 : <dir>
cpufreq : <dir>
cpuidle : <dir>
hotplug : <dir>
intel_pstate : <dir>
kernel_max : 15
microcode : <dir>
modalias : cpu:type:x86,ven0000fam0006mod005C:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,002B,0034,003A,003B,003D,0068,006A,006B,006C,006D,006F,0070,0072,0074,0075,0076,0078,007C,007D,0080,0081,0082,0083,0084,0085,0087,0088,0089,008B,008D,008E,008F,0093,0094,0095,0096,0097,0098,0099,009A,009B,009E,00C0,00C8,00EF,0100,0101,0102,0103,0104,0120,0121,0127,0129,012D,012E,012F,0132,0134,0137,0139,013D,0140,0141,0142,0143,01C0,01C1,01C2,01C4,01C6
online : 0-3
possible : 0-3
power : <dir>
present : 0-3
/sys/devices/system/cpu/cpufreq
policy0 : <dir>
policy1 : <dir>
policy2 : <dir>
policy3 : <dir>
/sys/devices/system/cpu/cpu0/cpufreq
affected_cpus : 0
cpuinfo_cur_freq : 2173461
cpuinfo_max_freq : 2300000
cpuinfo_min_freq : 800000
cpuinfo_transition_latency : 4294967295
related_cpus : 0
scaling_available_governors : performance powersave
scaling_cur_freq : 2199920
scaling_driver : intel_pstate
scaling_governor : powersave
scaling_max_freq : 2300000
scaling_min_freq : 800000
scaling_setspeed : <unsupported>
/sys/devices/system/cpu/cpu1/cpufreq
affected_cpus : 1
cpuinfo_cur_freq : 2199920
cpuinfo_max_freq : 2300000
cpuinfo_min_freq : 800000
cpuinfo_transition_latency : 4294967295
related_cpus : 1
scaling_available_governors : performance powersave
scaling_cur_freq : 2152770
scaling_driver : intel_pstate
scaling_governor : powersave
scaling_max_freq : 2300000
scaling_min_freq : 800000
scaling_setspeed : <unsupported>
/sys/devices/system/cpu/cpu2/cpufreq
affected_cpus : 2
cpuinfo_cur_freq : 2025787
cpuinfo_max_freq : 2300000
cpuinfo_min_freq : 800000
cpuinfo_transition_latency : 4294967295
related_cpus : 2
scaling_available_governors : performance powersave
scaling_cur_freq : 2026336
scaling_driver : intel_pstate
scaling_governor : powersave
scaling_max_freq : 2300000
scaling_min_freq : 800000
scaling_setspeed : <unsupported>
/sys/devices/system/cpu/cpu3/cpufreq
affected_cpus : 3
cpuinfo_cur_freq : 2070281
cpuinfo_max_freq : 2300000
cpuinfo_min_freq : 800000
cpuinfo_transition_latency : 4294967295
related_cpus : 3
scaling_available_governors : performance powersave
scaling_cur_freq : 2047943
scaling_driver : intel_pstate
scaling_governor : powersave
scaling_max_freq : 2300000
scaling_min_freq : 800000
scaling_setspeed : <unsupported>
################################################################################
# ... output of cat /proc/meminfo
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
MemTotal: 3426544 kB
MemFree: 2614020 kB
MemAvailable: 2893032 kB
Buffers: 50888 kB
Cached: 542560 kB
SwapCached: 0 kB
Active: 269680 kB
Inactive: 472168 kB
Active(anon): 200856 kB
Inactive(anon): 203204 kB
Active(file): 68824 kB
Inactive(file): 268964 kB
Unevictable: 0 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 236 kB
Writeback: 28 kB
AnonPages: 148388 kB
Mapped: 61020 kB
Shmem: 255532 kB
Slab: 29984 kB
SReclaimable: 15020 kB
SUnreclaim: 14964 kB
KernelStack: 3168 kB
PageTables: 2224 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 1713272 kB
Committed_AS: 844180 kB
VmallocTotal: 34359738367 kB
VmallocUsed: 0 kB
VmallocChunk: 0 kB
AnonHugePages: 0 kB
ShmemHugePages: 0 kB
ShmemPmdMapped: 0 kB
DirectMap4k: 19808 kB
DirectMap2M: 1464320 kB
DirectMap1G: 4194304 kB
[-- Attachment #3: 02_System.log --]
[-- Type: application/octet-stream, Size: 63994 bytes --]
################################################################################
# ... output of dmesg
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
[ 0.000000] Linux version 4.9.0-rc5+ (root@kompilator) (gcc version 5.4.0 (GCC) ) #1 SMP Sun Nov 20 05:29:03 CET 2016
[ 0.000000] Command line: BOOT_IMAGE=/KERNEL boot=LABEL=System disk=LABEL=Storage quiet
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
[ 0.000000] x86/fpu: xstate_offset[3]: 576, xstate_sizes[3]: 64
[ 0.000000] x86/fpu: xstate_offset[4]: 640, xstate_sizes[4]: 64
[ 0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 704 bytes, using 'compacted' format.
[ 0.000000] x86/fpu: Using 'eager' FPU context switches.
[ 0.000000] e820: BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000003efff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000003f000-0x000000000003ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000040000-0x000000000009dfff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable
[ 0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000012151000-0x000000005b4d7fff] usable
[ 0.000000] BIOS-e820: [mem 0x000000005b4d8000-0x000000005d5cdfff] reserved
[ 0.000000] BIOS-e820: [mem 0x000000005d5ce000-0x000000005d9a9fff] usable
[ 0.000000] BIOS-e820: [mem 0x000000005d9aa000-0x000000005d9e0fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000005d9e1000-0x000000005ddddfff] reserved
[ 0.000000] BIOS-e820: [mem 0x000000005ddde000-0x000000005e154fff] usable
[ 0.000000] BIOS-e820: [mem 0x000000005e155000-0x000000005e155fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000005e156000-0x000000005e17ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x000000005e180000-0x000000005e756fff] usable
[ 0.000000] BIOS-e820: [mem 0x000000005e757000-0x000000005e758fff] reserved
[ 0.000000] BIOS-e820: [mem 0x000000005e759000-0x000000005effffff] usable
[ 0.000000] BIOS-e820: [mem 0x000000005f000000-0x000000007fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d0000000-0x00000000d0ffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fe042000-0x00000000fe044fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fe900000-0x00000000fe902fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000017fffffff] usable
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] e820: update [mem 0x567f6018-0x56806057] usable ==> usable
[ 0.000000] e820: update [mem 0x567e7018-0x567f5057] usable ==> usable
[ 0.000000] extended physical RAM map:
[ 0.000000] reserve setup_data: [mem 0x0000000000000000-0x000000000003efff] usable
[ 0.000000] reserve setup_data: [mem 0x000000000003f000-0x000000000003ffff] reserved
[ 0.000000] reserve setup_data: [mem 0x0000000000040000-0x000000000009dfff] usable
[ 0.000000] reserve setup_data: [mem 0x000000000009e000-0x00000000000fffff] reserved
[ 0.000000] reserve setup_data: [mem 0x0000000000100000-0x000000000fffffff] usable
[ 0.000000] reserve setup_data: [mem 0x0000000010000000-0x0000000012150fff] reserved
[ 0.000000] reserve setup_data: [mem 0x0000000012151000-0x00000000567e7017] usable
[ 0.000000] reserve setup_data: [mem 0x00000000567e7018-0x00000000567f5057] usable
[ 0.000000] reserve setup_data: [mem 0x00000000567f5058-0x00000000567f6017] usable
[ 0.000000] reserve setup_data: [mem 0x00000000567f6018-0x0000000056806057] usable
[ 0.000000] reserve setup_data: [mem 0x0000000056806058-0x000000005b4d7fff] usable
[ 0.000000] reserve setup_data: [mem 0x000000005b4d8000-0x000000005d5cdfff] reserved
[ 0.000000] reserve setup_data: [mem 0x000000005d5ce000-0x000000005d9a9fff] usable
[ 0.000000] reserve setup_data: [mem 0x000000005d9aa000-0x000000005d9e0fff] ACPI NVS
[ 0.000000] reserve setup_data: [mem 0x000000005d9e1000-0x000000005ddddfff] reserved
[ 0.000000] reserve setup_data: [mem 0x000000005ddde000-0x000000005e154fff] usable
[ 0.000000] reserve setup_data: [mem 0x000000005e155000-0x000000005e155fff] ACPI NVS
[ 0.000000] reserve setup_data: [mem 0x000000005e156000-0x000000005e17ffff] reserved
[ 0.000000] reserve setup_data: [mem 0x000000005e180000-0x000000005e756fff] usable
[ 0.000000] reserve setup_data: [mem 0x000000005e757000-0x000000005e758fff] reserved
[ 0.000000] reserve setup_data: [mem 0x000000005e759000-0x000000005effffff] usable
[ 0.000000] reserve setup_data: [mem 0x000000005f000000-0x000000007fffffff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000d0000000-0x00000000d0ffffff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000e0000000-0x00000000efffffff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000fe042000-0x00000000fe044fff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000fe900000-0x00000000fe902fff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000fed01000-0x00000000fed01fff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[ 0.000000] reserve setup_data: [mem 0x00000000ff800000-0x00000000ffffffff] reserved
[ 0.000000] reserve setup_data: [mem 0x0000000100000000-0x000000017fffffff] usable
[ 0.000000] efi: EFI v2.50 by American Megatrends
[ 0.000000] efi: ESRT=0x5dd82918 ACPI=0x5d9aa000 ACPI 2.0=0x5d9aa000 SMBIOS=0x5dc4f000 SMBIOS 3.0=0x5dc4e000
[ 0.000000] SMBIOS 3.0.0 present.
[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.000000] e820: last_pfn = 0x180000 max_arch_pfn = 0x400000000
[ 0.000000] MTRR default type: uncachable
[ 0.000000] MTRR fixed ranges enabled:
[ 0.000000] 00000-6FFFF write-back
[ 0.000000] 70000-7FFFF uncachable
[ 0.000000] 80000-9FFFF write-back
[ 0.000000] A0000-BFFFF uncachable
[ 0.000000] C0000-FFFFF write-protect
[ 0.000000] MTRR variable ranges enabled:
[ 0.000000] 0 base 0000000000 mask 7FC0000000 write-back
[ 0.000000] 1 base 0040000000 mask 7FE0000000 write-back
[ 0.000000] 2 base 005F000000 mask 7FFF000000 uncachable
[ 0.000000] 3 base 0100000000 mask 7F80000000 write-back
[ 0.000000] 4 base 00FF800000 mask 7FFF800000 write-combining
[ 0.000000] 5 disabled
[ 0.000000] 6 disabled
[ 0.000000] 7 disabled
[ 0.000000] 8 disabled
[ 0.000000] 9 disabled
[ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT
[ 0.000000] e820: last_pfn = 0x5f000 max_arch_pfn = 0x400000000
[ 0.000000] esrt: Reserving ESRT space from 0x000000005dd82918 to 0x000000005dd82950.
[ 0.000000] Scanning 1 areas for low memory corruption
[ 0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576
[ 0.000000] Using GB pages for direct mapping
[ 0.000000] BRK [0x0332f000, 0x0332ffff] PGTABLE
[ 0.000000] BRK [0x03330000, 0x03330fff] PGTABLE
[ 0.000000] BRK [0x03331000, 0x03331fff] PGTABLE
[ 0.000000] BRK [0x03332000, 0x03332fff] PGTABLE
[ 0.000000] BRK [0x03333000, 0x03333fff] PGTABLE
[ 0.000000] BRK [0x03334000, 0x03334fff] PGTABLE
[ 0.000000] ACPI: Early table checksum verification disabled
[ 0.000000] ACPI: RSDP 0x000000005D9AA000 000024 (v02 ALASKA)
[ 0.000000] ACPI: XSDT 0x000000005D9AA0C0 0000EC (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.000000] ACPI: FACP 0x000000005D9B3210 000114 (v06 ALASKA A M I 01072009 AMI 00010013)
[ 0.000000] ACPI: DSDT 0x000000005D9AA250 008FB3 (v02 ALASKA A M I 01072009 INTL 20120913)
[ 0.000000] ACPI: FACS 0x000000005D9C8080 000040
[ 0.000000] ACPI: FPDT 0x000000005D9B3330 000044 (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.000000] ACPI: FIDT 0x000000005D9B3380 00009C (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.000000] ACPI: MCFG 0x000000005D9B3420 00003C (v01 ALASKA A M I 01072009 MSFT 00000097)
[ 0.000000] ACPI: DBG2 0x000000005D9B3460 000072 (v00 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: DBGP 0x000000005D9B34E0 000034 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: HPET 0x000000005D9B3520 000038 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: LPIT 0x000000005D9B3560 00005C (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: APIC 0x000000005D9B35C0 000084 (v03 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: NPKT 0x000000005D9B3650 000065 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: PRAM 0x000000005D9B36C0 000030 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: WSMT 0x000000005D9B36F0 000028 (v00 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: SSDT 0x000000005D9B3720 000B53 (v02 INTEL UsbCTabl 00000003 BRXT 0100000D)
[ 0.000000] ACPI: SSDT 0x000000005D9B4280 0016E9 (v01 Intel_ Platform 00001000 INTL 20120913)
[ 0.000000] ACPI: AAFT 0x000000005D9B5970 0002DA (v01 ALASKA OEMAAFT 01072009 MSFT 00000097)
[ 0.000000] ACPI: SSDT 0x000000005D9B5C50 000442 (v02 PmRef Cpu0Ist 00003000 INTL 20120913)
[ 0.000000] ACPI: SSDT 0x000000005D9B60A0 00072B (v02 CpuRef CpuSsdt 00003000 INTL 20120913)
[ 0.000000] ACPI: SSDT 0x000000005D9B67D0 00032D (v02 PmRef Cpu0Tst 00003000 INTL 20120913)
[ 0.000000] ACPI: SSDT 0x000000005D9B6B00 00017C (v02 PmRef ApTst 00003000 INTL 20120913)
[ 0.000000] ACPI: SSDT 0x000000005D9B6C80 002760 (v02 SaSsdt SaSsdt 00003000 INTL 20120913)
[ 0.000000] ACPI: UEFI 0x000000005D9B93E0 000042 (v01 ALASKA A M I 00000000 00000000)
[ 0.000000] ACPI: BGRT 0x000000005D9B9430 000038 (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.000000] ACPI: TPM2 0x000000005D9B9470 000034 (v03 Tpm2Tabl 00000001 AMI 00000000)
[ 0.000000] ACPI: WDAT 0x000000005D9B94B0 000104 (v01 00000000 00000000)
[ 0.000000] ACPI: NHLT 0x000000005D9B95C0 001A50 (v00 INTEL EDK2 00000002 01000013)
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] No NUMA configuration found
[ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000017fffffff]
[ 0.000000] NODE_DATA(0) allocated [mem 0x17fff7000-0x17fffafff]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff]
[ 0.000000] Normal [mem 0x0000000100000000-0x000000017fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000001000-0x000000000003efff]
[ 0.000000] node 0: [mem 0x0000000000040000-0x000000000009dfff]
[ 0.000000] node 0: [mem 0x0000000000100000-0x000000000fffffff]
[ 0.000000] node 0: [mem 0x0000000012151000-0x000000005b4d7fff]
[ 0.000000] node 0: [mem 0x000000005d5ce000-0x000000005d9a9fff]
[ 0.000000] node 0: [mem 0x000000005ddde000-0x000000005e154fff]
[ 0.000000] node 0: [mem 0x000000005e180000-0x000000005e756fff]
[ 0.000000] node 0: [mem 0x000000005e759000-0x000000005effffff]
[ 0.000000] node 0: [mem 0x0000000100000000-0x000000017fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000017fffffff]
[ 0.000000] On node 0 totalpages: 895220
[ 0.000000] DMA zone: 64 pages used for memmap
[ 0.000000] DMA zone: 22 pages reserved
[ 0.000000] DMA zone: 3996 pages, LIFO batch:0
[ 0.000000] DMA32 zone: 5734 pages used for memmap
[ 0.000000] DMA32 zone: 366936 pages, LIFO batch:31
[ 0.000000] Normal zone: 8192 pages used for memmap
[ 0.000000] Normal zone: 524288 pages, LIFO batch:31
[ 0.000000] Reserving Intel graphics memory at 0x0000000060000000-0x000000007fffffff
[ 0.000000] ACPI: PM-Timer IO Port: 0x408
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
[ 0.000000] ACPI: IRQ0 used by override.
[ 0.000000] ACPI: IRQ9 used by override.
[ 0.000000] Using ACPI (MADT) for SMP configuration information
[ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
[ 0.000000] e820: [mem 0x80000000-0xcfffffff] available for PCI devices
[ 0.000000] Booting paravirtualized kernel on bare hardware
[ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370452778343963 ns
[ 0.000000] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
[ 0.000000] percpu: Embedded 33 pages/cpu @ffff88017fc00000 s95256 r8192 d31720 u524288
[ 0.000000] pcpu-alloc: s95256 r8192 d31720 u524288 alloc=1*2097152
[ 0.000000] pcpu-alloc: [0] 0 1 2 3
[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 881208
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: root=/dev/ram0 rdinit=/init usbcore.autosuspend=-1 BOOT_IMAGE=/KERNEL boot=LABEL=System disk=LABEL=Storage quiet
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Memory: 3343564K/3580880K available (9656K kernel code, 798K rwdata, 19296K rodata, 4068K init, 392K bss, 237316K reserved, 0K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
[ 0.000000] NR_IRQS:4352 nr_irqs:1024 16
[ 0.000000] Console: colour dummy device 80x25
[ 0.000000] console [tty0] enabled
[ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns
[ 0.000000] hpet clockevent registered
[ 0.000000] tsc: PIT calibration matches HPET. 1 loops
[ 0.000000] tsc: Detected 1497.587 MHz processor
[ 0.000093] Calibrating delay loop (skipped), value calculated using timer frequency.. 2996.00 BogoMIPS (lpj=4992000)
[ 0.000097] pid_max: default: 32768 minimum: 301
[ 0.000110] ACPI: Core revision 20160831
[ 0.013988] ACPI: 8 ACPI AML tables successfully acquired and loaded
[ 0.015558] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.017313] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.018108] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.018120] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.018537] CPU: Physical Processor ID: 0
[ 0.018540] CPU: Processor Core ID: 0
[ 0.018565] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0
[ 0.018567] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
[ 0.019660] Freeing SMP alternatives memory: 40K (ffffffff832c2000 - ffffffff832cc000)
[ 0.036689] smpboot: APIC(0) Converting physical 0 to logical package 0
[ 0.036691] smpboot: Max logical packages: 1
[ 0.041269] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.074288] TSC deadline timer enabled
[ 0.074297] smpboot: CPU0: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz (family: 0x6, model: 0x5c, stepping: 0x9)
[ 0.074304] Performance Events: PEBS fmt3+, Goldmont events, 32-deep LBR, full-width counters, Intel PMU driver.
[ 0.074333] ... version: 4
[ 0.074334] ... bit width: 48
[ 0.074335] ... generic registers: 4
[ 0.074336] ... value mask: 0000ffffffffffff
[ 0.074337] ... max period: 0000ffffffffffff
[ 0.074338] ... fixed-purpose events: 3
[ 0.074339] ... event mask: 000000070000000f
[ 0.075020] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
[ 0.075200] x86: Booting SMP configuration:
[ 0.075203] .... node #0, CPUs: #1 #2 #3
[ 0.326691] x86: Booted up 1 node, 4 CPUs
[ 0.326694] smpboot: Total of 4 processors activated (11996.77 BogoMIPS)
[ 0.328959] devtmpfs: initialized
[ 0.329428] PM: Registering ACPI NVS region [mem 0x5d9aa000-0x5d9e0fff] (225280 bytes)
[ 0.329434] PM: Registering ACPI NVS region [mem 0x5e155000-0x5e155fff] (4096 bytes)
[ 0.329518] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370867519511994 ns
[ 0.329559] xor: measuring software checksum speed
[ 0.361898] prefetch64-sse: 7906.800 MB/sec
[ 0.395272] generic_sse: 6810.000 MB/sec
[ 0.395274] xor: using function: prefetch64-sse (7906.800 MB/sec)
[ 0.395301] pinctrl core: initialized pinctrl subsystem
[ 0.395557] NET: Registered protocol family 16
[ 0.405298] cpuidle: using governor ladder
[ 0.418654] cpuidle: using governor menu
[ 0.418876] ACPI: bus type PCI registered
[ 0.418980] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.418984] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
[ 0.419003] PCI: Using configuration type 1 for base access
[ 0.488725] raid6: sse2x1 gen() 3255 MB/s
[ 0.545459] raid6: sse2x1 xor() 1936 MB/s
[ 0.602158] raid6: sse2x2 gen() 3753 MB/s
[ 0.658911] raid6: sse2x2 xor() 2320 MB/s
[ 0.715632] raid6: sse2x4 gen() 4300 MB/s
[ 0.772341] raid6: sse2x4 xor() 2089 MB/s
[ 0.772343] raid6: using algorithm sse2x4 gen() 4300 MB/s
[ 0.772344] raid6: .... xor() 2089 MB/s, rmw enabled
[ 0.772346] raid6: using ssse3x2 recovery algorithm
[ 0.772414] ACPI: Added _OSI(Module Device)
[ 0.772416] ACPI: Added _OSI(Processor Device)
[ 0.772417] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 0.772418] ACPI: Added _OSI(Processor Aggregator Device)
[ 0.773028] ACPI: Executed 3 blocks of module-level executable AML code
[ 0.783279] ACPI: Dynamic OEM Table Load:
[ 0.783291] ACPI: SSDT 0xFFFF88017AD93E00 000102 (v02 PmRef Cpu0Cst 00003001 INTL 20120913)
[ 0.784016] ACPI: Dynamic OEM Table Load:
[ 0.784026] ACPI: SSDT 0xFFFF88017ADD6000 00015F (v02 PmRef ApIst 00003000 INTL 20120913)
[ 0.784428] ACPI: Dynamic OEM Table Load:
[ 0.784437] ACPI: SSDT 0xFFFF88017AD80600 00008D (v02 PmRef ApCst 00003000 INTL 20120913)
[ 0.786348] ACPI: Interpreter enabled
[ 0.786384] ACPI: (supports S0 S3 S5)
[ 0.786386] ACPI: Using IOAPIC for interrupt routing
[ 0.786514] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 0.803643] ACPI: Power Resource [FN00] (on)
[ 0.804893] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[ 0.804902] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
[ 0.805989] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[ 0.806258] PCI host bridge to bus 0000:00
[ 0.806262] pci_bus 0000:00: root bus resource [io 0x0070-0x0077]
[ 0.806265] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window]
[ 0.806267] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window]
[ 0.806269] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 0.806272] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 0.806274] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
[ 0.806276] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000fffff window]
[ 0.806278] pci_bus 0000:00: root bus resource [mem 0x60000001-0x7fffffff window]
[ 0.806281] pci_bus 0000:00: root bus resource [mem 0x5f800001-0x5fffffff window]
[ 0.806283] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window]
[ 0.806285] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window]
[ 0.806288] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.806308] pci 0000:00:00.0: [8086:5af0] type 00 class 0x060000
[ 0.806786] pci 0000:00:02.0: [8086:5a85] type 00 class 0x030000
[ 0.806804] pci 0000:00:02.0: reg 0x10: [mem 0x90000000-0x90ffffff 64bit]
[ 0.806815] pci 0000:00:02.0: reg 0x18: [mem 0x80000000-0x8fffffff 64bit pref]
[ 0.806824] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f]
[ 0.807319] pci 0000:00:0e.0: [8086:5a98] type 00 class 0x040300
[ 0.807344] pci 0000:00:0e.0: reg 0x10: [mem 0x91310000-0x91313fff 64bit]
[ 0.807373] pci 0000:00:0e.0: reg 0x20: [mem 0x91000000-0x910fffff 64bit]
[ 0.807438] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold
[ 0.807849] pci 0000:00:0e.0: System wakeup disabled by ACPI
[ 0.807921] pci 0000:00:0f.0: [8086:5a9a] type 00 class 0x078000
[ 0.807961] pci 0000:00:0f.0: reg 0x10: [mem 0x9131b000-0x9131bfff 64bit]
[ 0.808094] pci 0000:00:0f.0: PME# supported from D3hot
[ 0.808493] pci 0000:00:12.0: [8086:5ae3] type 00 class 0x010601
[ 0.808513] pci 0000:00:12.0: reg 0x10: [mem 0x91314000-0x91315fff]
[ 0.808524] pci 0000:00:12.0: reg 0x14: [mem 0x91318000-0x913180ff]
[ 0.808534] pci 0000:00:12.0: reg 0x18: [io 0xf090-0xf097]
[ 0.808546] pci 0000:00:12.0: reg 0x1c: [io 0xf080-0xf083]
[ 0.808556] pci 0000:00:12.0: reg 0x20: [io 0xf060-0xf07f]
[ 0.808566] pci 0000:00:12.0: reg 0x24: [mem 0x91317000-0x913177ff]
[ 0.808623] pci 0000:00:12.0: PME# supported from D3hot
[ 0.808992] pci 0000:00:13.0: [8086:5ad8] type 01 class 0x060400
[ 0.809082] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold
[ 0.809394] pci 0000:00:13.0: System wakeup disabled by ACPI
[ 0.809458] pci 0000:00:13.1: [8086:5ad9] type 01 class 0x060400
[ 0.809547] pci 0000:00:13.1: PME# supported from D0 D3hot D3cold
[ 0.809859] pci 0000:00:13.1: System wakeup disabled by ACPI
[ 0.809922] pci 0000:00:13.2: [8086:5ada] type 01 class 0x060400
[ 0.810010] pci 0000:00:13.2: PME# supported from D0 D3hot D3cold
[ 0.810330] pci 0000:00:13.2: System wakeup disabled by ACPI
[ 0.810399] pci 0000:00:13.3: [8086:5adb] type 01 class 0x060400
[ 0.810488] pci 0000:00:13.3: PME# supported from D0 D3hot D3cold
[ 0.810801] pci 0000:00:13.3: System wakeup disabled by ACPI
[ 0.810883] pci 0000:00:15.0: [8086:5aa8] type 00 class 0x0c0330
[ 0.810907] pci 0000:00:15.0: reg 0x10: [mem 0x91300000-0x9130ffff 64bit]
[ 0.810981] pci 0000:00:15.0: PME# supported from D3hot D3cold
[ 0.811318] pci 0000:00:15.0: System wakeup disabled by ACPI
[ 0.811440] pci 0000:00:1f.0: [8086:5ae8] type 00 class 0x060100
[ 0.811938] pci 0000:00:1f.1: [8086:5ad4] type 00 class 0x0c0500
[ 0.811993] pci 0000:00:1f.1: reg 0x10: [mem 0x91316000-0x913160ff 64bit]
[ 0.812073] pci 0000:00:1f.1: reg 0x20: [io 0xf040-0xf05f]
[ 0.812602] pci 0000:01:00.0: [10ec:8168] type 00 class 0x020000
[ 0.812627] pci 0000:01:00.0: reg 0x10: [io 0xe000-0xe0ff]
[ 0.812663] pci 0000:01:00.0: reg 0x18: [mem 0x91204000-0x91204fff 64bit]
[ 0.812684] pci 0000:01:00.0: reg 0x20: [mem 0x91200000-0x91203fff 64bit pref]
[ 0.812704] pci 0000:01:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug
[ 0.812811] pci 0000:01:00.0: supports D1 D2
[ 0.812813] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 0.812884] pci 0000:01:00.0: System wakeup disabled by ACPI
[ 0.823764] pci 0000:00:13.0: PCI bridge to [bus 01]
[ 0.823769] pci 0000:00:13.0: bridge window [io 0xe000-0xefff]
[ 0.823774] pci 0000:00:13.0: bridge window [mem 0x91200000-0x912fffff]
[ 0.823837] pci 0000:00:13.1: PCI bridge to [bus 02]
[ 0.823920] pci 0000:03:00.0: [1b21:0612] type 00 class 0x010601
[ 0.823945] pci 0000:03:00.0: reg 0x10: [io 0xd050-0xd057]
[ 0.823959] pci 0000:03:00.0: reg 0x14: [io 0xd040-0xd043]
[ 0.823972] pci 0000:03:00.0: reg 0x18: [io 0xd030-0xd037]
[ 0.823986] pci 0000:03:00.0: reg 0x1c: [io 0xd020-0xd023]
[ 0.824000] pci 0000:03:00.0: reg 0x20: [io 0xd000-0xd01f]
[ 0.824015] pci 0000:03:00.0: reg 0x24: [mem 0x91100000-0x911001ff]
[ 0.824157] pci 0000:03:00.0: System wakeup disabled by ACPI
[ 0.833765] pci 0000:00:13.2: PCI bridge to [bus 03]
[ 0.833770] pci 0000:00:13.2: bridge window [io 0xd000-0xdfff]
[ 0.833775] pci 0000:00:13.2: bridge window [mem 0x91100000-0x911fffff]
[ 0.833835] pci 0000:00:13.3: PCI bridge to [bus 04]
[ 0.835611] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.835716] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.835820] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.835922] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.836025] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.836128] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.836230] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.836333] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.837519] ACPI: Enabled 4 GPEs in block 00 to 7F
[ 0.837822] pci 0000:00:02.0: vgaarb: setting as boot VGA device
[ 0.837827] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[ 0.837833] pci 0000:00:02.0: vgaarb: bridge control possible
[ 0.837835] vgaarb: loaded
[ 0.837979] SCSI subsystem initialized
[ 0.838071] libata version 3.00 loaded.
[ 0.838107] ACPI: bus type USB registered
[ 0.838142] usbcore: registered new interface driver usbfs
[ 0.838162] usbcore: registered new interface driver hub
[ 0.838195] usbcore: registered new device driver usb
[ 0.838242] pps_core: LinuxPPS API ver. 1 registered
[ 0.838243] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.838247] PTP clock support registered
[ 0.838311] Registered efivars operations
[ 0.866324] Advanced Linux Sound Architecture Driver Initialized.
[ 0.866325] PCI: Using ACPI for IRQ routing
[ 0.894545] PCI: pci_cache_line_size set to 64 bytes
[ 0.894623] e820: reserve RAM buffer [mem 0x0003f000-0x0003ffff]
[ 0.894625] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
[ 0.894627] e820: reserve RAM buffer [mem 0x567e7018-0x57ffffff]
[ 0.894628] e820: reserve RAM buffer [mem 0x567f6018-0x57ffffff]
[ 0.894630] e820: reserve RAM buffer [mem 0x5b4d8000-0x5bffffff]
[ 0.894631] e820: reserve RAM buffer [mem 0x5d9aa000-0x5fffffff]
[ 0.894633] e820: reserve RAM buffer [mem 0x5e155000-0x5fffffff]
[ 0.894635] e820: reserve RAM buffer [mem 0x5e757000-0x5fffffff]
[ 0.894637] e820: reserve RAM buffer [mem 0x5f000000-0x5fffffff]
[ 0.894962] clocksource: Switched to clocksource hpet
[ 0.895088] pnp: PnP ACPI init
[ 0.895523] system 00:00: [io 0x0280-0x028f] has been reserved
[ 0.895526] system 00:00: [io 0x0290-0x029f] has been reserved
[ 0.895528] system 00:00: [io 0x02a0-0x02af] has been reserved
[ 0.895535] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.896060] pnp 00:01: [dma 0 disabled]
[ 0.896150] pnp 00:01: Plug and Play ACPI device, IDs PNP0501 (active)
[ 0.896246] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.897028] system 00:03: [io 0x0680-0x069f] has been reserved
[ 0.897031] system 00:03: [io 0x0400-0x047f] has been reserved
[ 0.897034] system 00:03: [io 0x0500-0x05fe] has been reserved
[ 0.897038] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.897613] system 00:04: [mem 0xe0000000-0xefffffff] has been reserved
[ 0.897616] system 00:04: [mem 0xfea00000-0xfeafffff] has been reserved
[ 0.897619] system 00:04: [mem 0xfed01000-0xfed01fff] has been reserved
[ 0.897621] system 00:04: [mem 0xfed03000-0xfed03fff] has been reserved
[ 0.897624] system 00:04: [mem 0xfed06000-0xfed06fff] has been reserved
[ 0.897627] system 00:04: [mem 0xfed08000-0xfed09fff] has been reserved
[ 0.897629] system 00:04: [mem 0xfed80000-0xfedbffff] has been reserved
[ 0.897632] system 00:04: [mem 0xfed1c000-0xfed1cfff] has been reserved
[ 0.897635] system 00:04: [mem 0xfee00000-0xfeefffff] could not be reserved
[ 0.897639] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.897865] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 0.898152] pnp: PnP ACPI: found 6 devices
[ 0.907996] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[ 0.908056] pci 0000:00:13.0: PCI bridge to [bus 01]
[ 0.908060] pci 0000:00:13.0: bridge window [io 0xe000-0xefff]
[ 0.908067] pci 0000:00:13.0: bridge window [mem 0x91200000-0x912fffff]
[ 0.908076] pci 0000:00:13.1: PCI bridge to [bus 02]
[ 0.908087] pci 0000:00:13.2: PCI bridge to [bus 03]
[ 0.908091] pci 0000:00:13.2: bridge window [io 0xd000-0xdfff]
[ 0.908096] pci 0000:00:13.2: bridge window [mem 0x91100000-0x911fffff]
[ 0.908104] pci 0000:00:13.3: PCI bridge to [bus 04]
[ 0.908117] pci_bus 0000:00: resource 4 [io 0x0070-0x0077]
[ 0.908120] pci_bus 0000:00: resource 5 [io 0x0000-0x006f window]
[ 0.908122] pci_bus 0000:00: resource 6 [io 0x0078-0x0cf7 window]
[ 0.908124] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window]
[ 0.908127] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
[ 0.908129] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
[ 0.908131] pci_bus 0000:00: resource 10 [mem 0x000e0000-0x000fffff window]
[ 0.908134] pci_bus 0000:00: resource 11 [mem 0x60000001-0x7fffffff window]
[ 0.908136] pci_bus 0000:00: resource 12 [mem 0x5f800001-0x5fffffff window]
[ 0.908138] pci_bus 0000:00: resource 13 [mem 0x80000000-0xcfffffff window]
[ 0.908141] pci_bus 0000:00: resource 14 [mem 0xe0000000-0xefffffff window]
[ 0.908143] pci_bus 0000:01: resource 0 [io 0xe000-0xefff]
[ 0.908146] pci_bus 0000:01: resource 1 [mem 0x91200000-0x912fffff]
[ 0.908148] pci_bus 0000:03: resource 0 [io 0xd000-0xdfff]
[ 0.908150] pci_bus 0000:03: resource 1 [mem 0x91100000-0x911fffff]
[ 0.908368] NET: Registered protocol family 2
[ 0.908608] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
[ 0.908810] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
[ 0.909083] TCP: Hash tables configured (established 32768 bind 32768)
[ 0.909141] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[ 0.909196] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[ 0.909328] NET: Registered protocol family 1
[ 0.909539] RPC: Registered named UNIX socket transport module.
[ 0.909540] RPC: Registered udp transport module.
[ 0.909541] RPC: Registered tcp transport module.
[ 0.909542] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.909564] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[ 0.909614] pci 0000:00:15.0: enabling device (0000 -> 0002)
[ 0.910019] PCI: CLS 0 bytes, default 64
[ 0.985513] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[ 0.985521] software IO TLB [mem 0x527e6000-0x567e6000] (64MB) mapped at [ffff8800527e6000-ffff8800567e5fff]
[ 0.985769] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer
[ 0.985771] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules
[ 0.985772] RAPL PMU: hw unit of domain package 2^-14 Joules
[ 0.985773] RAPL PMU: hw unit of domain dram 2^-14 Joules
[ 0.985774] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules
[ 0.986279] Scanning for low memory corruption every 60 seconds
[ 0.986645] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 0.987068] workingset: timestamp_bits=40 max_order=20 bucket_order=0
[ 0.990634] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.990928] NFS: Registering the id_resolver key type
[ 0.990941] Key type id_resolver registered
[ 0.990942] Key type id_legacy registered
[ 0.990946] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 0.993630] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
[ 0.993633] io scheduler noop registered
[ 0.993720] io scheduler cfq registered (default)
[ 0.995035] pcieport 0000:00:13.0: Signaling PME through PCIe PME interrupt
[ 0.995038] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[ 0.995042] pcie_pme 0000:00:13.0:pcie001: service driver pcie_pme loaded
[ 0.995072] pcieport 0000:00:13.1: Signaling PME through PCIe PME interrupt
[ 0.995076] pcie_pme 0000:00:13.1:pcie001: service driver pcie_pme loaded
[ 0.995112] pcieport 0000:00:13.2: Signaling PME through PCIe PME interrupt
[ 0.995114] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt
[ 0.995119] pcie_pme 0000:00:13.2:pcie001: service driver pcie_pme loaded
[ 0.995149] pcieport 0000:00:13.3: Signaling PME through PCIe PME interrupt
[ 0.995153] pcie_pme 0000:00:13.3:pcie001: service driver pcie_pme loaded
[ 0.995184] efifb: probing for efifb
[ 0.995210] efifb: framebuffer at 0x80000000, using 3072k, total 3072k
[ 0.995211] efifb: mode is 1024x768x32, linelength=4096, pages=1
[ 0.995212] efifb: scrolling: redraw
[ 0.995214] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
[ 0.999882] Console: switching to colour frame buffer device 128x48
[ 1.004356] fb0: EFI VGA frame buffer device
[ 1.004369] intel_idle: MWAIT substates: 0x11242020
[ 1.004371] intel_idle: v0.4.1 model 0x5C
[ 1.004774] intel_idle: lapic_timer_reliable_states 0xffffffff
[ 1.004883] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
[ 1.004888] ACPI: Power Button [PWRB]
[ 1.008763] thermal LNXTHERM:00: registered as thermal_zone0
[ 1.008765] ACPI: Thermal Zone [TZ01] (39 C)
[ 1.009024] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 1.029885] 00:01: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
[ 1.030864] [drm] Initialized
[ 1.031452] [drm] Memory usable by graphics device = 4096M
[ 1.031455] checking generic (80000000 300000) vs hw (80000000 10000000)
[ 1.031457] fb: switching to inteldrmfb from EFI VGA
[ 1.031497] Console: switching to colour dummy device 80x25
[ 1.031695] [drm] Replacing VGA console driver
[ 1.032059] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 1.032060] [drm] Driver supports precise vblank timestamp query.
[ 1.034761] [drm] Finished loading i915/bxt_dmc_ver1_07.bin (v1.7)
[ 1.035204] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
[ 1.998337] tsc: Refined TSC clocksource calibration: 1497.599 MHz
[ 1.998349] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x1596467b3e4, max_idle_ns: 440795260276 ns
[ 2.024334] [drm] failed to retrieve link info, disabling eDP
[ 2.045784] [drm] GuC firmware load skipped
[ 2.066401] random: fast init done
[ 2.090391] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no)
[ 2.091278] acpi device:10: registered as cooling_device5
[ 2.091381] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input1
[ 2.091435] [drm] Initialized i915 1.6.0 20161108 for 0000:00:02.0 on minor 0
[ 2.093802] ------------[ cut here ]------------
[ 2.093812] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_dp.c:4068 intel_dp_check_link_status+0x1a5/0x1d0
[ 2.093813] WARN_ON_ONCE(!intel_dp->lane_count)
[ 2.093815] Modules linked in:
[ 2.093820] CPU: 0 PID: 6 Comm: kworker/u8:0 Not tainted 4.9.0-rc5+ #1
[ 2.093822] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./J3455-ITX, BIOS P1.10 09/29/2016
[ 2.093827] Workqueue: events_unbound async_run_entry_fn
[ 2.093830] 0000000000000000 ffffffff8138d075 ffff88017b337c88 0000000000000000
[ 2.093834] ffffffff8104ac94 ffff88017a6fc0f0 ffff88017b337cd8 ffff88017a6fc000
[ 2.093838] ffff88017a750258 ffff88017a6fc0f0 ffff88017a6fc000 ffffffff8104acfb
[ 2.093842] Call Trace:
[ 2.093849] [<ffffffff8138d075>] ? dump_stack+0x5c/0x77
[ 2.093852] [<ffffffff8104ac94>] ? __warn+0xb4/0xd0
[ 2.093855] [<ffffffff8104acfb>] ? warn_slowpath_fmt+0x4b/0x50
[ 2.093858] [<ffffffff81473cfb>] ? drm_dp_dpcd_read+0x4b/0x60
[ 2.093861] [<ffffffff81537715>] ? intel_dp_check_link_status+0x1a5/0x1d0
[ 2.093865] [<ffffffff8153d3b7>] ? intel_dp_detect+0x5c7/0xa10
[ 2.093868] [<ffffffff81474921>] ? drm_helper_probe_single_connector_modes+0x3f1/0x4d0
[ 2.093871] [<ffffffff8148299a>] ? drm_fb_helper_initial_config+0x7a/0x410
[ 2.093874] [<ffffffff8107e719>] ? pick_next_task_fair+0x139/0x480
[ 2.093878] [<ffffffff8152ef5f>] ? intel_fbdev_initial_config+0xf/0x20
[ 2.093881] [<ffffffff810677dd>] ? async_run_entry_fn+0x2d/0xe0
[ 2.093884] [<ffffffff8105f687>] ? process_one_work+0x137/0x410
[ 2.093886] [<ffffffff8105f9a6>] ? worker_thread+0x46/0x4e0
[ 2.093889] [<ffffffff8105f960>] ? process_one_work+0x410/0x410
[ 2.093892] [<ffffffff8106504a>] ? kthread+0xba/0xd0
[ 2.093895] [<ffffffff81064f90>] ? kthread_park+0x50/0x50
[ 2.093899] [<ffffffff8196a405>] ? ret_from_fork+0x25/0x30
[ 2.093905] ---[ end trace e3370de1682602bf ]---
[ 2.095648] brd: module loaded
[ 2.095697] loop: module loaded
[ 2.097681] fbcon: inteldrmfb (fb0) is primary device
[ 2.099762] nbd: registered device at major 43
[ 2.102509] usbcore: registered new interface driver rtsx_usb
[ 2.102524] Loading iSCSI transport class v2.0-870.
[ 2.102740] iscsi: registered transport (tcp)
[ 2.102742] megasas: 06.811.02.00-rc1
[ 2.103006] ahci 0000:00:12.0: version 3.0
[ 2.103018] ahci 0000:00:12.0: enabling device (0000 -> 0003)
[ 2.103306] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
[ 2.103310] ahci 0000:00:12.0: flags: 64bit ncq sntf clo only pmp pio slum part deso sadm sds apst
[ 2.104049] scsi host0: ahci
[ 2.104537] scsi host1: ahci
[ 2.104618] ata1: SATA max UDMA/133 abar m2048@0x91317000 port 0x91317100 irq 19
[ 2.104622] ata2: SATA max UDMA/133 abar m2048@0x91317000 port 0x91317180 irq 19
[ 2.104792] ahci 0000:03:00.0: SSS flag set, parallel bus scan disabled
[ 2.104856] ahci 0000:03:00.0: AHCI 0001.0200 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
[ 2.104860] ahci 0000:03:00.0: flags: 64bit ncq sntf stag led clo pmp pio slum part ccc
[ 2.105563] scsi host2: ahci
[ 2.105908] scsi host3: ahci
[ 2.105976] ata3: SATA max UDMA/133 abar m512@0x91100000 port 0x91100100 irq 20
[ 2.105980] ata4: SATA max UDMA/133 abar m512@0x91100000 port 0x91100180 irq 20
[ 2.106523] tun: Universal TUN/TAP device driver, 1.6
[ 2.106524] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
[ 2.106693] pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de
[ 2.106722] Atheros(R) L2 Ethernet Driver - version 2.2.3
[ 2.106723] Copyright (c) 2007 Atheros Corporation.
[ 2.106826] cnic: QLogic cnicDriver v2.5.22 (July 20, 2015)
[ 2.106934] uli526x: ULi M5261/M5263 net driver, version 0.9.3 (2005-7-29)
[ 2.106952] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
[ 2.106953] e100: Copyright(c) 1999-2006 Intel Corporation
[ 2.106971] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.106972] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.106994] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[ 2.106995] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 2.107017] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.4.0-k
[ 2.107018] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.107036] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 4.4.0-k
[ 2.107037] ixgbe: Copyright (c) 1999-2016 Intel Corporation.
[ 2.107187] ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
[ 2.107188] ixgb: Copyright (c) 1999-2008 Intel Corporation.
[ 2.107208] jme: JMicron JMC2XX ethernet driver version 1.0.8
[ 2.107243] sky2: driver version 1.30
[ 2.107329] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
[ 2.115993] r8169 0000:01:00.0 eth0: RTL8168g/8111g at 0xffffc900007fc000, 70:85:c2:21:0e:91, XID 0c000800 IRQ 125
[ 2.115996] r8169 0000:01:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko]
[ 2.116150] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 2.116151] ehci-pci: EHCI PCI platform driver
[ 2.116170] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 2.116177] ohci-pci: OHCI PCI platform driver
[ 2.116191] uhci_hcd: USB Universal Host Controller Interface driver
[ 2.116446] xhci_hcd 0000:00:15.0: xHCI Host Controller
[ 2.116455] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1
[ 2.117614] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x01009810
[ 2.117623] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
[ 2.117996] hub 1-0:1.0: USB hub found
[ 2.118013] hub 1-0:1.0: 8 ports detected
[ 2.119226] xhci_hcd 0000:00:15.0: xHCI Host Controller
[ 2.119232] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2
[ 2.119469] hub 2-0:1.0: USB hub found
[ 2.119490] hub 2-0:1.0: 7 ports detected
[ 2.120603] usbcore: registered new interface driver uas
[ 2.120630] usbcore: registered new interface driver usb-storage
[ 2.120679] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 2.124123] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 2.124131] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 2.124409] mousedev: PS/2 mouse device common for all mice
[ 2.124937] rtc_cmos 00:05: RTC can wake from S4
[ 2.125533] rtc_cmos 00:05: rtc core: registered rtc_cmos as rtc0
[ 2.125627] rtc_cmos 00:05: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
[ 2.125644] i2c /dev entries driver
[ 2.126151] i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A
[ 2.126153] i801_smbus 0000:00:1f.1: PCI INT A: not connected
[ 2.126178] i801_smbus 0000:00:1f.1: SPD Write Disable is set
[ 2.126202] i801_smbus 0000:00:1f.1: Failed to allocate irq -2147483648: -107
[ 2.126203] i801_smbus 0000:00:1f.1: SMBus using polling
[ 2.126923] intel_pstate: Intel P-state driver initializing
[ 2.127303] sdhci: Secure Digital Host Controller Interface driver
[ 2.127304] sdhci: Copyright(c) Pierre Ossman
[ 2.127369] No iBFT detected.
[ 2.127372] EFI Variables Facility v0.08 2004-May-17
[ 2.160025] hidraw: raw HID events driver (C) Jiri Kosina
[ 2.160330] usbcore: registered new interface driver usbhid
[ 2.160331] usbhid: USB HID core driver
[ 2.160765] NET: Registered protocol family 10
[ 2.161224] NET: Registered protocol family 17
[ 2.161253] Key type dns_resolver registered
[ 2.161434] microcode: sig=0x506c9, pf=0x1, revision=0x1c
[ 2.161728] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[ 2.162882] Btrfs loaded, crc32c=crc32c-generic
[ 2.180392] Console: switching to colour frame buffer device 240x67
[ 2.200630] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[ 2.200700] console [netcon0] enabled
[ 2.200701] netconsole: network logging started
[ 2.200898] rtc_cmos 00:05: setting system clock to 2016-11-20 13:31:03 UTC (1479648663)
[ 2.201067] ALSA device list:
[ 2.201069] No soundcards found.
[ 2.415068] ata3: SATA link down (SStatus 0 SControl 300)
[ 2.415083] ata1: SATA link down (SStatus 4 SControl 300)
[ 2.415228] ata2: SATA link down (SStatus 4 SControl 300)
[ 2.438432] usb 1-3: new low-speed USB device number 2 using xhci_hcd
[ 2.592185] input: PHILIPS OVU710023 as /devices/pci0000:00/0000:00:15.0/usb1/1-3/1-3:1.0/0003:0471:2168.0001/input/input5
[ 2.649510] hid-generic 0003:0471:2168.0001: input,hiddev0,hidraw0: USB HID v1.11 Keyboard [PHILIPS OVU710023] on usb-0000:00:15.0-3/input0
[ 2.761761] usb 1-4: new low-speed USB device number 3 using xhci_hcd
[ 2.881766] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 2.882482] ata4.00: ATA-8: Goldendisk GDSA-16GB, 20121211, max UDMA/133
[ 2.882487] ata4.00: 30916608 sectors, multi 0: LBA48
[ 2.883469] ata4.00: configured for UDMA/133
[ 2.883898] scsi 3:0:0:0: Direct-Access ATA Goldendisk GDSA- 1211 PQ: 0 ANSI: 5
[ 2.903601] input: Dell Dell USB Keyboard as /devices/pci0000:00/0000:00:15.0/usb1/1-4/1-4:1.0/0003:413C:2003.0002/input/input6
[ 2.918961] sd 3:0:0:0: Attached scsi generic sg0 type 0
[ 2.918976] sd 3:0:0:0: [sda] 30916608 512-byte logical blocks: (15.8 GB/14.7 GiB)
[ 2.919251] sd 3:0:0:0: [sda] Write Protect is off
[ 2.919258] sd 3:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.919492] sd 3:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 2.923580] sda: sda1 sda2
[ 2.924607] sd 3:0:0:0: [sda] Attached SCSI disk
[ 2.932657] Freeing unused kernel memory: 4068K (ffffffff82ec9000 - ffffffff832c2000)
[ 2.932660] Write protecting the kernel read-only data: 30720k
[ 2.933623] Freeing unused kernel memory: 568K (ffff880001972000 - ffff880001a00000)
[ 2.938695] Freeing unused kernel memory: 1184K (ffff880002cd8000 - ffff880002e00000)
[ 2.966465] hid-generic 0003:413C:2003.0002: input,hidraw1: USB HID v1.10 Keyboard [Dell Dell USB Keyboard] on usb-0000:00:15.0-4/input0
[ 3.012098] clocksource: Switched to clocksource tsc
[ 3.078326] usb 1-6: new full-speed USB device number 4 using xhci_hcd
[ 3.217798] input: Microsoft Microsoft® Nano Transceiver v2.0 as /devices/pci0000:00/0000:00:15.0/usb1/1-6/1-6:1.0/0003:045E:0745.0003/input/input7
[ 3.272103] hid-generic 0003:045E:0745.0003: input,hidraw2: USB HID v1.11 Keyboard [Microsoft Microsoft® Nano Transceiver v2.0] on usb-0000:00:15.0-6/input0
[ 3.278494] input: Microsoft Microsoft® Nano Transceiver v2.0 as /devices/pci0000:00/0000:00:15.0/usb1/1-6/1-6:1.1/0003:045E:0745.0004/input/input8
[ 3.331945] [drm] RC6 on
[ 3.335629] hid-generic 0003:045E:0745.0004: input,hidraw3: USB HID v1.11 Mouse [Microsoft Microsoft® Nano Transceiver v2.0] on usb-0000:00:15.0-6/input1
[ 3.351815] input: Microsoft Microsoft® Nano Transceiver v2.0 as /devices/pci0000:00/0000:00:15.0/usb1/1-6/1-6:1.2/0003:045E:0745.0005/input/input9
[ 3.408743] hid-generic 0003:045E:0745.0005: input,hiddev0,hidraw4: USB HID v1.11 Device [Microsoft Microsoft® Nano Transceiver v2.0] on usb-0000:00:15.0-6/input2
[ 4.252487] EXT4-fs (sda2): couldn't mount as ext3 due to feature incompatibilities
[ 4.252780] EXT4-fs (sda2): couldn't mount as ext2 due to feature incompatibilities
[ 4.259664] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[ 6.672696] systemd[1]: systemd 230 running in system mode. (-PAM -AUDIT -SELINUX -IMA -APPARMOR -SMACK -SYSVINIT -UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS -ACL -XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN)
[ 6.672958] systemd[1]: Detected architecture x86-64.
[ 6.673104] systemd[1]: Set hostname to <LibreELEC>.
[ 6.696759] systemd[1]: Configuration file /storage/.config/system.d/storage-videos.mount is marked executable. Please remove executable permission bits. Proceeding anyway.
[ 6.697588] systemd[1]: Configuration file /storage/.config/system.d/storage-tvshows.mount is marked executable. Please remove executable permission bits. Proceeding anyway.
[ 6.697958] systemd[1]: storage-tvshows.mount: Where= setting doesn't match unit name. Refusing.
[ 6.698174] systemd[1]: storage-tvshows.mount: Cannot add dependency job, ignoring: Unit storage-tvshows.mount is not loaded properly: Invalid argument.
[ 6.698796] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
[ 6.698917] systemd[1]: Listening on Journal Socket.
[ 6.698979] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[ 6.765346] systemd-journald[226]: Received request to flush runtime journal from PID 1
[ 6.832371] random: crng init done
[ 7.206810] snd_soc_skl 0000:00:0e.0: bound 0000:00:02.0 (ops 0xffffffff81aa4ec0)
[ 7.213760] snd_soc_skl 0000:00:0e.0: No matching machine driver found
[ 7.217582] r8169 0000:01:00.0 eth0: link down
[ 7.217604] r8169 0000:01:00.0 eth0: link down
[ 7.217757] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 7.219024] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops 0xffffffff81aa4ec0)
[ 7.249400] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC892: line_outs=3 (0x14/0x15/0x16/0x0/0x0) type:line
[ 7.249403] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
[ 7.249405] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x1b/0x0/0x0/0x0/0x0)
[ 7.249407] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0
[ 7.249408] snd_hda_codec_realtek hdaudioC0D0: dig-out=0x1e/0x0
[ 7.249409] snd_hda_codec_realtek hdaudioC0D0: inputs:
[ 7.249412] snd_hda_codec_realtek hdaudioC0D0: Front Mic=0x19
[ 7.249413] snd_hda_codec_realtek hdaudioC0D0: Rear Mic=0x18
[ 7.249415] snd_hda_codec_realtek hdaudioC0D0: Line=0x1a
[ 7.257578] intel_rapl: Found RAPL domain package
[ 7.257582] intel_rapl: Found RAPL domain core
[ 7.257586] intel_rapl: Found RAPL domain uncore
[ 7.257589] intel_rapl: Found RAPL domain dram
[ 8.297497] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:0e.0/sound/card0/input10
[ 8.298265] input: HDA Intel PCH Front Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input11
[ 8.298353] input: HDA Intel PCH Rear Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input12
[ 8.298423] input: HDA Intel PCH Line as /devices/pci0000:00/0000:00:0e.0/sound/card0/input13
[ 8.298486] input: HDA Intel PCH Line Out Front as /devices/pci0000:00/0000:00:0e.0/sound/card0/input14
[ 8.298554] input: HDA Intel PCH Line Out Surround as /devices/pci0000:00/0000:00:0e.0/sound/card0/input15
[ 8.298648] input: HDA Intel PCH Line Out CLFE as /devices/pci0000:00/0000:00:0e.0/sound/card0/input16
[ 8.298715] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input17
[ 8.298795] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input18
[ 8.298862] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input19
[ 8.298929] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input20
[ 10.165215] r8169 0000:01:00.0 eth0: link up
[ 10.165233] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 10.169830] 8021q: 802.1Q VLAN Support v1.8
[ 11.989694] snd_hda_intel 0000:00:0e.0: IRQ timing workaround is activated for card #0. Suggest a bigger bdl_pos_adj.
################################################################################
# ... output of lsmod
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
Module Size Used by
8021q 17727 0
snd_hda_codec_hdmi 33057 1
intel_rapl 10176 0
snd_hda_codec_realtek 56387 1
snd_hda_codec_generic 53990 1 snd_hda_codec_realtek
snd_hda_intel 20580 3
snd_hda_codec 82254 4 snd_hda_intel,snd_hda_codec_hdmi,snd_hda_codec_generic,snd_hda_codec_realtek
snd_hwdep 5418 1 snd_hda_codec
snd_soc_skl 38434 0
snd_soc_sst_match 1426 1 snd_soc_skl
snd_soc_skl_ipc 24174 1 snd_soc_skl
snd_soc_sst_ipc 3550 1 snd_soc_skl_ipc
snd_soc_sst_dsp 5766 1 snd_soc_skl_ipc
snd_hda_ext_core 9489 1 snd_soc_skl
snd_hda_core 43137 7 snd_hda_intel,snd_hda_codec,snd_hda_ext_core,snd_soc_skl,snd_hda_codec_hdmi,snd_hda_codec_generic,snd_hda_codec_realtek
snd_soc_rt286 29641 0
snd_soc_rt298 29384 0
snd_soc_rl6347a 1514 2 snd_soc_rt298,snd_soc_rt286
################################################################################
# ... output of ps xa
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
PID USER TIME COMMAND
1 root 0:01 /usr/lib/systemd/systemd
2 root 0:00 [kthreadd]
3 root 0:00 [ksoftirqd/0]
4 root 0:00 [kworker/0:0]
5 root 0:00 [kworker/0:0H]
6 root 0:00 [kworker/u8:0]
7 root 0:00 [rcu_sched]
8 root 0:00 [rcu_bh]
9 root 0:00 [migration/0]
10 root 0:00 [lru-add-drain]
11 root 0:00 [watchdog/0]
12 root 0:00 [cpuhp/0]
13 root 0:00 [cpuhp/1]
14 root 0:00 [watchdog/1]
15 root 0:00 [migration/1]
16 root 0:00 [ksoftirqd/1]
17 root 0:00 [kworker/1:0]
18 root 0:00 [kworker/1:0H]
19 root 0:00 [cpuhp/2]
20 root 0:00 [watchdog/2]
21 root 0:00 [migration/2]
22 root 0:00 [ksoftirqd/2]
23 root 0:00 [kworker/2:0]
24 root 0:00 [kworker/2:0H]
25 root 0:00 [cpuhp/3]
26 root 0:00 [watchdog/3]
27 root 0:00 [migration/3]
28 root 0:00 [ksoftirqd/3]
29 root 0:00 [kworker/3:0]
30 root 0:00 [kworker/3:0H]
31 root 0:00 [kdevtmpfs]
32 root 0:00 [netns]
33 root 0:00 [khungtaskd]
34 root 0:00 [oom_reaper]
35 root 0:00 [writeback]
36 root 0:00 [kcompactd0]
37 root 0:00 [khugepaged]
38 root 0:00 [crypto]
39 root 0:00 [bioset]
40 root 0:00 [kblockd]
41 root 0:00 [kworker/0:1]
42 root 0:00 [kworker/1:1]
43 root 0:00 [ata_sff]
44 root 0:00 [kworker/3:1]
45 root 0:00 [rpciod]
46 root 0:00 [xprtiod]
47 root 0:00 [kswapd0]
48 root 0:00 [vmstat]
49 root 0:00 [nfsiod]
50 root 0:00 [cifsiod]
66 root 0:00 [acpi_thermal_pm]
67 root 0:00 [kworker/u8:1]
68 root 0:00 [kworker/3:2]
69 root 0:00 [i915/signal:0]
70 root 0:00 [i915/signal:1]
71 root 0:00 [i915/signal:2]
72 root 0:00 [i915/signal:4]
73 root 0:00 [kworker/2:1]
74 root 0:00 [bioset]
75 root 0:00 [bioset]
76 root 0:00 [bioset]
77 root 0:00 [bioset]
78 root 0:00 [bioset]
79 root 0:00 [bioset]
80 root 0:00 [bioset]
81 root 0:00 [bioset]
82 root 0:00 [bioset]
83 root 0:00 [bioset]
84 root 0:00 [bioset]
85 root 0:00 [bioset]
86 root 0:00 [bioset]
87 root 0:00 [bioset]
88 root 0:00 [bioset]
89 root 0:00 [bioset]
90 root 0:00 [bioset]
91 root 0:00 [bioset]
92 root 0:00 [bioset]
93 root 0:00 [bioset]
94 root 0:00 [bioset]
95 root 0:00 [bioset]
96 root 0:00 [bioset]
97 root 0:00 [bioset]
98 root 0:00 [bioset]
99 root 0:00 [bioset]
100 root 0:00 [bioset]
101 root 0:00 [bioset]
102 root 0:00 [bioset]
103 root 0:00 [bioset]
104 root 0:00 [bioset]
105 root 0:00 [bioset]
106 root 0:00 [iscsi_eh]
107 root 0:00 [nvme]
108 root 0:00 [scsi_eh_0]
109 root 0:00 [scsi_tmf_0]
110 root 0:00 [scsi_eh_1]
111 root 0:00 [scsi_tmf_1]
112 root 0:00 [kworker/u8:2]
113 root 0:00 [kworker/u8:3]
114 root 0:00 [scsi_eh_2]
115 root 0:00 [scsi_tmf_2]
116 root 0:00 [scsi_eh_3]
117 root 0:00 [scsi_tmf_3]
118 root 0:00 [kworker/u8:4]
119 root 0:00 [kworker/u8:5]
120 root 0:00 [cnic_wq]
121 root 0:00 [ixgbe]
122 root 0:00 [kworker/2:2]
123 root 0:00 [kworker/u8:6]
124 root 0:00 [ipv6_addrconf]
125 root 0:00 [bioset]
126 root 0:00 [bioset]
152 root 0:00 [kworker/3:1H]
155 root 0:00 [kworker/2:3]
157 root 0:00 [kworker/2:1H]
158 root 0:00 [kworker/0:1H]
165 root 0:00 [jbd2/sda2-8]
166 root 0:00 [ext4-rsv-conver]
177 root 0:00 [kworker/1:1H]
179 root 0:00 [bioset]
180 root 0:00 [loop0]
218 root 0:00 [kworker/3:3]
223 root 0:00 [kworker/0:2]
226 root 0:00 /usr/lib/systemd/systemd-journald
238 root 0:00 [kworker/1:2]
252 root 0:00 /usr/lib/systemd/systemd-udevd
254 root 0:00 /usr/lib/systemd/systemd-logind
268 root 0:00 /usr/sbin/eventlircd -f --evmap=/etc/eventlircd.d --socket=/run/lirc/lircd --release=_UP
270 root 0:00 /usr/bin/pulseaudio --system
272 dbus 0:00 /usr/bin/dbus-daemon --system --address=systemd: --nofork --nopidfile --systemd-activation
280 root 0:00 /sbin/crond -f -S
287 root 0:00 /usr/sbin/sshd -D
298 root 0:00 /usr/sbin/connmand -nr --config=/etc/connman/main.conf
307 avahi 0:00 avahi-daemon: running [LibreELEC.local]
308 root 0:00 /usr/bin/rpcbind
312 root 0:00 /usr/sbin/unfsd -d -e /storage/.config/exports
321 root 0:00 /usr/bin/wpa_supplicant -u
352 root 0:00 /usr/bin/nmbd --configfile=/run/samba/smb.conf
356 root 0:00 [kworker/1:3]
570 root 0:00 /usr/bin/smbd --configfile=/run/samba/smb.conf
575 root 0:00 [kworker/1:4]
721 root 0:00 [lockd]
724 root 0:00 xorg-launch-helper -nolisten tcp vt01 -s 0 -noreset -allowMouseOpenFail
726 root 0:00 /usr/bin/Xorg -nolisten tcp vt01 -s 0 -noreset -allowMouseOpenFail
735 root 0:00 /usr/bin/fluxbox
740 root 0:00 {kodi.sh} /bin/sh /usr/lib/kodi/kodi.sh --standalone -fs --lircdev /run/lirc/lircd
745 root 0:02 /usr/lib/kodi/kodi.bin --standalone -fs --lircdev /run/lirc/lircd
799 root 0:00 /usr/bin/smbd --configfile=/run/samba/smb.conf
808 root 0:00 sh -c createlog
809 root 0:00 {createlog} /bin/sh /usr/bin/createlog
838 root 0:00 ps xa
################################################################################
# ... output of cat /storage/.config/modprobe.d/alsa-base.conf
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
options snd-hda-intel power_save=0 power_save_controller=N
################################################################################
# ... output of cat /storage/.config/modprobe.d/disable-spdif-for-hd-audio.conf
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
# INTEL HBR WORKAROUND FOR DTS-MA & Dolby TrueHD PLAYBACK
# Uncomment the following lines to disable any S/PDIF out to deliver
# bitstreamed audio on Intel builds. This is a rough workaround for
# users that have both S/PDIF and HDMI audio outputs on their motherboard
# or motherboard+discrete graphics combo.
# EVEN IF YOU ARE NOT USING THE S/PDIF OUTPUT
# but still have one, you will need to uncomment the lines below !
# after uncommenting these lines, you must reboot for these settings to take effect
#blacklist snd_hda_codec_realtek
#blacklist snd_soc_skl
#blacklist snd_hda_codec_generic
#blacklist snd_hda_intel
# blacklist snd_hda_codec_sigmatel
# blacklist snd_hda_codec_cirrus
# blacklist snd_soc_skl
################################################################################
# ... output of cat /storage/.config/sysctl.d/transmission.conf
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
# transmission with uTP support
# please comment out the follow line to activate this values:
# net.core.wmem_max=1048576
# net.core.rmem_max=4194304
################################################################################
# ... output of ls -laR /storage/.config/system.d
# LibreELEC release: Generic.x86_64-devel-20161120
# LibreELEC git: 2e3081a9304242b3d10c78d55f673dfd1824da0d
################################################################################
/storage/.config/system.d:
total 64
drwxr-xr-x 3 root root 4096 Nov 19 16:13 .
drwxr-xr-x 14 root root 4096 Nov 19 22:12 ..
-rw-r--r-- 1 root root 28816 Oct 26 20:24 README
-rw-r--r-- 1 root root 1772 Oct 26 20:24 cifs.mount.sample
drwxr-xr-x 2 root root 4096 Nov 19 16:07 multi-user.target.wants
-rw-r--r-- 1 root root 1729 Nov 19 16:13 nfs.mount.sample
-rw-r--r-- 1 root root 1145 Oct 26 20:24 openvpn.service.sample
-rwxr--r-- 1 root root 1737 Nov 19 16:06 storage-tvshows.mount
-rwxr--r-- 1 root root 1736 Nov 19 16:05 storage-videos.mount
/storage/.config/system.d/multi-user.target.wants:
total 8
drwxr-xr-x 2 root root 4096 Nov 19 16:07 .
drwxr-xr-x 3 root root 4096 Nov 19 16:13 ..
lrwxrwxrwx 1 root root 47 Nov 19 16:07 storage-tvshows.mount -> /storage/.config/system.d/storage-tvshows.mount
lrwxrwxrwx 1 root root 46 Nov 19 16:07 storage-videos.mount -> /storage/.config/system.d/storage-videos.mount
[-- Attachment #4: Type: text/plain, Size: 81 bytes --]
Thanks
For any help or info where i can raport bug
Best regards
Piotr Kasprzak
^ permalink raw reply
* Re: [patch v9 1/1] i2c: add master driver for mellanox systems
From: Wolfram Sang @ 2016-11-24 14:52 UTC (permalink / raw)
To: vadimp; +Cc: wsa, linux-i2c, linux-kernel, jiri, Michael Shych
In-Reply-To: <1479660974-143713-1-git-send-email-vadimp@mellanox.com>
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On Sun, Nov 20, 2016 at 04:56:14PM +0000, vadimp@mellanox.com wrote:
> From: Vadim Pasternak <vadimp@mellanox.com>
>
> Device driver for Mellanox I2C controller logic, implemented in Lattice
> CPLD device.
> Device supports:
> - Master mode
> - One physical bus
> - Polling mode
>
> The Kconfig currently controlling compilation of this code is:
> drivers/i2c/busses/Kconfig:config I2C_MLXCPLD
>
> Signed-off-by: Michael Shych <michaelsh@mellanox.com>
> Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
> Reviewed-by: Jiri Pirko <jiri@mellanox.com>
> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Applied to for-next, thanks!
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^ permalink raw reply
* Re: [PATCH v5 6/6] i2c: use an IRQ to report Host Notify events, not alert
From: Wolfram Sang @ 2016-11-24 15:06 UTC (permalink / raw)
To: Benjamin Tissoires
Cc: Wolfram Sang, Dmitry Torokhov, linux-i2c, linux-kernel,
Jean Delvare
In-Reply-To: <20161122114922.GA3993@katana>
[-- Attachment #1: Type: text/plain, Size: 1604 bytes --]
On Tue, Nov 22, 2016 at 12:49:22PM +0100, Wolfram Sang wrote:
> On Mon, Nov 21, 2016 at 11:52:48AM +0100, Benjamin Tissoires wrote:
> > Hi Wolfram,
> >
> > On Nov 07 2016 or thereabouts, Wolfram Sang wrote:
> > > On Thu, Oct 13, 2016 at 02:10:40PM +0200, Benjamin Tissoires wrote:
> > > > The current SMBus Host Notify implementation relies on .alert() to
> > > > relay its notifications. However, the use cases where SMBus Host
> > > > Notify is needed currently is to signal data ready on touchpads.
> > > >
> > > > This is closer to an IRQ than a custom API through .alert().
> > > > Given that the 2 touchpad manufacturers (Synaptics and Elan) that
> > > > use SMBus Host Notify don't put any data in the SMBus payload, the
> > > > concept actually matches one to one.
> > >
> > > I see the advantages. The only question I have: What if we encounter
> > > devices in the future which do put data in the payload? Can this
> > > mechanism be extended to handle that?
> >
> > I guess I haven't convinced you with my answer. Is there anything I can
> > do to get this series in v4.10 or do you prefer waiting for v4.11?
>
> I consider this v4.10 material. I was thinking a little about how to not
> lose data with consecutive interrupts but then -EBUSY came along.
> Nonetheless, it looks to me like the proper path to follow...
Applied to for-next, thanks!
Fixed the following checkpatch warning for you:
WARNING: struct irq_domain_ops should normally be const
#250: FILE: drivers/i2c/i2c-core.c:1838:
+static struct irq_domain_ops i2c_host_notify_irq_ops = {
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^ permalink raw reply
* Re: [PATCH v5 6/6] i2c: use an IRQ to report Host Notify events, not alert
From: Benjamin Tissoires @ 2016-11-24 15:10 UTC (permalink / raw)
To: Wolfram Sang
Cc: Wolfram Sang, Dmitry Torokhov, linux-i2c, linux-kernel,
Jean Delvare
In-Reply-To: <20161124150608.GE4271@katana>
On Nov 24 2016 or thereabouts, Wolfram Sang wrote:
> On Tue, Nov 22, 2016 at 12:49:22PM +0100, Wolfram Sang wrote:
> > On Mon, Nov 21, 2016 at 11:52:48AM +0100, Benjamin Tissoires wrote:
> > > Hi Wolfram,
> > >
> > > On Nov 07 2016 or thereabouts, Wolfram Sang wrote:
> > > > On Thu, Oct 13, 2016 at 02:10:40PM +0200, Benjamin Tissoires wrote:
> > > > > The current SMBus Host Notify implementation relies on .alert() to
> > > > > relay its notifications. However, the use cases where SMBus Host
> > > > > Notify is needed currently is to signal data ready on touchpads.
> > > > >
> > > > > This is closer to an IRQ than a custom API through .alert().
> > > > > Given that the 2 touchpad manufacturers (Synaptics and Elan) that
> > > > > use SMBus Host Notify don't put any data in the SMBus payload, the
> > > > > concept actually matches one to one.
> > > >
> > > > I see the advantages. The only question I have: What if we encounter
> > > > devices in the future which do put data in the payload? Can this
> > > > mechanism be extended to handle that?
> > >
> > > I guess I haven't convinced you with my answer. Is there anything I can
> > > do to get this series in v4.10 or do you prefer waiting for v4.11?
> >
> > I consider this v4.10 material. I was thinking a little about how to not
> > lose data with consecutive interrupts but then -EBUSY came along.
> > Nonetheless, it looks to me like the proper path to follow...
>
> Applied to for-next, thanks!
Thanks!
>
> Fixed the following checkpatch warning for you:
>
> WARNING: struct irq_domain_ops should normally be const
> #250: FILE: drivers/i2c/i2c-core.c:1838:
> +static struct irq_domain_ops i2c_host_notify_irq_ops = {
>
Thanks again :)
Cheers,
Benjamin
^ permalink raw reply
* Re: [PATCH v2] i2c: i2c-mux-gpio: update mux with gpiod_set_array_value_cansleep
From: Wolfram Sang @ 2016-11-24 15:14 UTC (permalink / raw)
To: Peter Rosin; +Cc: linux-kernel, Peter Korsgaard, Wolfram Sang, linux-i2c
In-Reply-To: <1479908035-18284-1-git-send-email-peda@axentia.se>
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Hi Peter,
> + int values[mux->data.n_gpios];
Hmm, my code checkers complain about this line:
CHECK drivers/i2c/muxes/i2c-mux-gpio.c
SPARSE
drivers/i2c/muxes/i2c-mux-gpio.c:29:29: warning: Variable length array is used.
SMATCH
drivers/i2c/muxes/i2c-mux-gpio.c:29:29: warning: Variable length array is used.
Worth to fix it?
BTW (unrelated to your patch), the compiler complains about:
In file included from drivers/i2c/muxes/i2c-mux-gpio.c:18:0:
drivers/i2c/muxes/../../gpio/gpiolib.h:88:27: warning: ‘gpio_suffixes’ defined but not used [-Wunused-const-variable=]
static const char * const gpio_suffixes[] = { "gpios", "gpio" };
which pointed out this line to me:
18 #include "../../gpio/gpiolib.h"
which is probably worth fixing, too?
Thanks,
Wolfram
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^ permalink raw reply
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