From: Boris Brezillon <boris.brezillon@collabora.com>
To: Conor Culhane <conor.culhane@silvaco.com>
Cc: linux-i3c@lists.infradead.org, bbrezillon@kernel.org
Subject: Re: [PATCH] i3c: master: Add driver for Silvaco I3C Dual-Role Master IP
Date: Thu, 16 Apr 2020 21:47:59 +0200 [thread overview]
Message-ID: <20200416214759.464139ca@collabora.com> (raw)
In-Reply-To: <20200411223843.631c7710@collabora.com>
On Sat, 11 Apr 2020 22:38:43 +0200
Boris Brezillon <boris.brezillon@collabora.com> wrote:
> +#define I3CS_CONFIG 0x004
> +#define I3CS_CONFIG_SLVENA BIT(0)
> +#define I3CS_CONFIG_NACK BIT(1)
> +#define I3CS_CONFIG_MATCHSS BIT(2)
> +#define I3CS_CONFIG_S0IGNORE BIT(3)
> +#define I3CS_CONFIG_DDROK BIT(4)
> +#define I3CS_CONFIG_IRAND BIT(8)
> +#define I3CS_CONFIG_BAMATCH(x) (((x) & GENMASK(7, 0)) << 16)
> +#define I3CS_CONFIG_SADDR(x) (((x) & GENMASK(6, 0)) << 25)
Just learned about the FIELD_{PREP,GET}() macros [1]. If you use them
you'll just have to define masks here.
[1]https://elixir.bootlin.com/linux/v5.7-rc1/source/include/linux/bitfield.h#L92
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prev parent reply other threads:[~2020-04-16 19:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-25 16:00 [PATCH] i3c: master: Add driver for Silvaco I3C Dual-Role Master IP Conor Culhane
2020-04-11 12:03 ` Boris Brezillon
2020-04-11 12:09 ` Boris Brezillon
2020-04-11 20:38 ` Boris Brezillon
2020-04-16 19:47 ` Boris Brezillon [this message]
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