Re: [PATCH 2/2] i3c/master: add the mipi-i3c-hci driver

kernel test robot
2020-08-15T09:18:26Z

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Hi Nicolas,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.8 next-20200813]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Nicolas-Pitre/MIPI-I3c-HCI-Host-Controller-Interface-driver/20200814-115156
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=sh

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

In file included from include/linux/scatterlist.h:9,
from include/linux/dma-mapping.h:11,
from drivers/i3c/master/mipi-i3c-hci/dma.c:13:
drivers/i3c/master/mipi-i3c-hci/dma.c: In function 'hci_dma_init':
>> drivers/i3c/master/mipi-i3c-hci/dma.c:252:48: warning: right shift count >= width of type [-Wshift-count-overflow]
252 | rh_reg_write(CMD_RING_BASE_HI, rh->xfer_phys >> 32);
| ^~
arch/sh/include/asm/io.h:33:77: note: in definition of macro '__raw_writel'
33 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
| ^
arch/sh/include/asm/io.h:48:62: note: in expansion of macro 'ioswabl'
48 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
| ^~~~~~~
arch/sh/include/asm/io.h:58:32: note: in expansion of macro 'writel_relaxed'
58 | #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
| ^~~~~~~~~~~~~~
drivers/i3c/master/mipi-i3c-hci/dma.c:56:28: note: in expansion of macro 'writel'
56 | #define rh_reg_write(r, v) writel(v, rh->regs + (RH_##r))
| ^~~~~~
drivers/i3c/master/mipi-i3c-hci/dma.c:252:3: note: in expansion of macro 'rh_reg_write'
252 | rh_reg_write(CMD_RING_BASE_HI, rh->xfer_phys >> 32);
| ^~~~~~~~~~~~
drivers/i3c/master/mipi-i3c-hci/dma.c:254:49: warning: right shift count >= width of type [-Wshift-count-overflow]
254 | rh_reg_write(RESP_RING_BASE_HI, rh->resp_phys >> 32);
| ^~
arch/sh/include/asm/io.h:33:77: note: in definition of macro '__raw_writel'
33 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
| ^
arch/sh/include/asm/io.h:48:62: note: in expansion of macro 'ioswabl'
48 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
| ^~~~~~~
arch/sh/include/asm/io.h:58:32: note: in expansion of macro 'writel_relaxed'
58 | #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
| ^~~~~~~~~~~~~~
drivers/i3c/master/mipi-i3c-hci/dma.c:56:28: note: in expansion of macro 'writel'
56 | #define rh_reg_write(r, v) writel(v, rh->regs + (RH_##r))
| ^~~~~~
drivers/i3c/master/mipi-i3c-hci/dma.c:254:3: note: in expansion of macro 'rh_reg_write'
254 | rh_reg_write(RESP_RING_BASE_HI, rh->resp_phys >> 32);
| ^~~~~~~~~~~~
drivers/i3c/master/mipi-i3c-hci/dma.c: In function 'hci_dma_queue_xfer':
drivers/i3c/master/mipi-i3c-hci/dma.c:388:35: warning: right shift count >= width of type [-Wshift-count-overflow]
388 | *ring_data++ = xfer->data_phys >> 32;
| ^~

vim +252 drivers/i3c/master/mipi-i3c-hci/dma.c

193
194 static int hci_dma_init(struct i3c_hci *hci)
195 {
196 struct hci_rings_data *rings;
197 struct hci_rh_data *rh;
198 u32 regval;
199 u_int i, nr_rings, xfers_sz, resps_sz;
200 u_int ibi_status_ring_sz, ibi_data_ring_sz;
201 int ret;
202
203 regval = rhs_reg_read(CONTROL);
204 nr_rings = FIELD_GET(MAX_HEADER_COUNT_CAP, regval);
205 INFO("%d DMA rings available", nr_rings);
206 if (unlikely(nr_rings > 8)) {
207 ERR("number of rings should be <= 8");
208 nr_rings = 8;
209 }
210 if (nr_rings > XFER_RINGS)
211 nr_rings = XFER_RINGS;
212 rings = kzalloc(sizeof(*rings) + nr_rings * sizeof(*rh), GFP_KERNEL);
213 if (!rings)
214 return -ENOMEM;
215 hci->io_data = rings;
216 rings->total = nr_rings;
217
218 for (i = 0; i < rings->total; i++) {
219 u32 offset = rhs_reg_read(RHn_OFFSET(i));
220
221 INFO("Ring %d at offset %#x", i, offset);
222 ret = -EINVAL;
223 if (!offset)
224 goto err_out;
225 rh = &rings->headers[i];
226 rh->regs = hci->base_regs + offset;
227 spin_lock_init(&rh->lock);
228 init_completion(&rh->op_done);
229
230 rh->xfer_entries = XFER_RING_ENTRIES;
231
232 regval = rh_reg_read(CR_SETUP);
233 rh->xfer_struct_sz = FIELD_GET(CR_XFER_STRUCT_SIZE, regval);
234 rh->resp_struct_sz = FIELD_GET(CR_RESP_STRUCT_SIZE, regval);
235 DBG("xfer_struct_sz = %d, resp_struct_sz = %d",
236 rh->xfer_struct_sz, rh->resp_struct_sz);
237 xfers_sz = rh->xfer_struct_sz * rh->xfer_entries;
238 resps_sz = rh->resp_struct_sz * rh->xfer_entries;
239
240 rh->xfer = dma_alloc_coherent(&hci->master.dev, xfers_sz,
241 &rh->xfer_phys, GFP_KERNEL);
242 rh->resp = dma_alloc_coherent(&hci->master.dev, resps_sz,
243 &rh->resp_phys, GFP_KERNEL);
244 rh->src_xfers =
245 kmalloc_array(rh->xfer_entries, sizeof(*rh->src_xfers),
246 GFP_KERNEL);
247 ret = -ENOMEM;
248 if (!rh->xfer || !rh->resp || !rh->src_xfers)
249 goto err_out;
250
251 rh_reg_write(CMD_RING_BASE_LO, rh->xfer_phys);
> 252 rh_reg_write(CMD_RING_BASE_HI, rh->xfer_phys >> 32);
253 rh_reg_write(RESP_RING_BASE_LO, rh->resp_phys);
254 rh_reg_write(RESP_RING_BASE_HI, rh->resp_phys >> 32);
255
256 regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);
257 rh_reg_write(CR_SETUP, regval);
258
259 rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
260 rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY |
261 INTR_TRANSFER_COMPLETION |
262 INTR_RING_OP |
263 INTR_TRANSFER_ERR |
264 INTR_WARN_INS_STOP_MODE |
265 INTR_IBI_RING_FULL |
266 INTR_TRANSFER_ABORT);
267
268 /* IBIs */
269
270 if (i >= IBI_RINGS)
271 goto ring_ready;
272
273 regval = rh_reg_read(IBI_SETUP);
274 rh->ibi_status_sz = FIELD_GET(IBI_STATUS_STRUCT_SIZE, regval);
275 rh->ibi_status_entries = IBI_STATUS_RING_ENTRIES;
276 rh->ibi_chunks_total = IBI_CHUNK_POOL_SIZE;
277
278 rh->ibi_chunk_sz = dma_get_cache_alignment();
279 rh->ibi_chunk_sz *= IBI_CHUNK_CACHELINES;
280 BUG_ON(rh->ibi_chunk_sz > 256);
281
282 ibi_status_ring_sz = rh->ibi_status_sz * rh->ibi_status_entries;
283 ibi_data_ring_sz = rh->ibi_chunk_sz * rh->ibi_chunks_total;
284
285 rh->ibi_status =
286 dma_alloc_coherent(&hci->master.dev, ibi_status_ring_sz,
287 &rh->ibi_status_phys, GFP_KERNEL);
288 rh->ibi_data = kmalloc(ibi_data_ring_sz, GFP_KERNEL);
289 ret = -ENOMEM;
290 if (!rh->ibi_status || !rh->ibi_data)
291 goto err_out;
292 rh->ibi_data_phys =
293 dma_map_single(&hci->master.dev, rh->ibi_data,
294 ibi_data_ring_sz, DMA_FROM_DEVICE);
295 if (dma_mapping_error(&hci->master.dev, rh->ibi_data_phys)) {
296 rh->ibi_data_phys = 0;
297 ret = -ENOMEM;
298 goto err_out;
299 }
300
301 regval = FIELD_PREP(IBI_STATUS_RING_SIZE,
302 rh->ibi_status_entries) |
303 FIELD_PREP(IBI_DATA_CHUNK_SIZE,
304 ilog2(rh->ibi_chunk_sz) - 2) |
305 FIELD_PREP(IBI_DATA_CHUNK_COUNT,
306 rh->ibi_chunks_total);
307 rh_reg_write(IBI_SETUP, regval);
308
309 regval = rh_reg_read(INTR_SIGNAL_ENABLE);
310 regval |= INTR_IBI_READY;
311 rh_reg_write(INTR_SIGNAL_ENABLE, regval);
312
313 ring_ready:
314 rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE);
315 }
316
317 regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total);
318 rhs_reg_write(CONTROL, regval);
319 return 0;
320
321 err_out:
322 hci_dma_cleanup(hci);
323 return ret;
324 }
325

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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