RE: [PATCH 0/4] i3c: master: svc: some bug fixes

Clark Wang
2021-07-30T19:40:38Z

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> -----Original Message-----
> From: Miquel Raynal <miquel.raynal@bootlin.com>
> Sent: Friday, July 16, 2021 15:52
> To: Clark Wang <xiaoning.wang@nxp.com>
> Cc: conor.culhane@silvaco.com; alexandre.belloni@bootlin.com;
> vitor.soares@synopsys.com; boris.brezillon@bootlin.com; linux-
> i3c@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 0/4] i3c: master: svc: some bug fixes
>
> Hi Clark,
>
> Clark Wang <xiaoning.wang@nxp.com> wrote on Thu, 15 Jul 2021 16:24:09
> +0800:
>
> > Hi,
> >
> > I am using SVC I3C module recently. I fix some problems and also have a
> > question.
> >
> > My question is:
> > Can I3C bus support pure I2C mode in kernel?
> > Or in other words, in mixed mode, must there be at least one I3C device on
> > the I3C bus?
> >
> > The pure I3C mode works fine. But when only have one I2C device on the
> > I3C bus, the probe in function i3c_master_bus_init() will go error. Because
> > there is no one on I3C bus can ACK the I3C message with I3C message
> speed. Then
> > it will return error at function i3c_master_rstdaa_locked() because of no
> ACK
> > for 0x7e start byte.
> > When I use the following dtb configuration, the above problem occurs.
> > &i3c2 {
> > #address-cells = <3>;
> > #size-cells = <0>;
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_i3c2>;
> > i2c-scl-hz = <400000>;
> > status = "okay";
> >
> > lsm6dso_i2c: imu@6a {
> > compatible = "st,lsm6dso";
> > reg = <0x6a 0x0 0x50>;
> > };
> > };
> >
> > But I saw a similar configuration example in
> >
> /home/nxf47749/work/kernel/i3c/Documentation/devicetree/bindings/i3c/
> snps,dw-i3c-master.txt.
> > I wonder if that can work normally?
> >
> > I know the definition in the specification is:
> > Mixed xxx Bus: I3C Bus topology with both I2C and I3C Devices present
> > on the I3C Bus...
> > But I think it is feasible to use pure I2C mode with I3C module.
> > I am not sure why the use of pure I2C mode is restricted in the software.
> >
> > If there are errors in my ideas, please correct me in time. Thank you all.
>
> As you pointed out, I am not aware of a specific I2C only bus setting
> but if you find a way to workaround the issue raised above by software
> in a rather clean way, then... why not?

Hi Miquel,

Ok. At present, I just commented part of the code for registering i3c for pure I2C mode testing. I will try to make a clean revision afterwards.
Thank you very much for your suggestion!

Best Regards,
Clark Wang

>
> > Here are the fixes.
> >
> > Clark Wang (4):
> > i3c: master: svc: move module reset behind clk enable
> > i3c: master: svc: fix atomic issue
> > i3c: master: svc: add support for slave to stop returning data
> > i3c: master: svc: set ODSTOP to let I2C device see the STOP signal
> >
> > drivers/i3c/master/svc-i3c-master.c | 45 +++++++++++++++++++----------
> > 1 file changed, 30 insertions(+), 15 deletions(-)
> >
>
> Thanks,
> Miquèl

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