Re: [PATCH v1 2/2] i3c: master: Add Nuvoton npcm845 i3c master driver

kernel test robot
2024-08-02T21:54:17Z

Hi Stanley,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.11-rc1 next-20240802]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Stanley-Chu/dt-bindings-i3c-Add-NPCM845-i3c-controller/20240802-183617
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240801071946.43266-3-yschu%40nuvoton.com
patch subject: [PATCH v1 2/2] i3c: master: Add Nuvoton npcm845 i3c master driver
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20240803/202408030543.PWRuy07u-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240803/202408030543.PWRuy07u-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408030543.PWRuy07u-lkp@intel.com/

All warnings (new ones prefixed by >>):

drivers/i3c/master/npcm845-i3c-master.c: In function 'npcm_i3c_master_bus_init':
>> drivers/i3c/master/npcm845-i3c-master.c:885:48: warning: left shift count >= width of type [-Wshift-count-overflow]
885 | info.pid = (NPCM_I3C_VENDORID_VID(reg) << 33) | readl(master->regs + NPCM_I3C_PARTNO);
| ^~
drivers/i3c/master/npcm845-i3c-master.c: At top level:
drivers/i3c/master/npcm845-i3c-master.c:2353:19: error: initialization of 'void (*)(struct platform_device *)' from incompatible pointer type 'int (*)(struct platform_device *)' [-Wincompatible-pointer-types]
2353 | .remove = npcm_i3c_master_remove,
| ^~~~~~~~~~~~~~~~~~~~~~
drivers/i3c/master/npcm845-i3c-master.c:2353:19: note: (near initialization for 'npcm_i3c_master.<anonymous>.remove')

vim +885 drivers/i3c/master/npcm845-i3c-master.c

770
771 static int npcm_i3c_master_bus_init(struct i3c_master_controller *m)
772 {
773 struct npcm_i3c_master *master = to_npcm_i3c_master(m);
774 struct i3c_bus *bus = i3c_master_get_bus(m);
775 struct i3c_device_info info = {};
776 unsigned long fclk_rate, fclk_period_ns;
777 unsigned long i3c_scl_rate, i2c_scl_rate;
778 unsigned int pp_high_period_ns, od_low_period_ns, i2c_period_ns;
779 unsigned int scl_period_ns;
780 u32 ppbaud, pplow, odhpp, odbaud, i2cbaud, reg;
781 int ret;
782
783 /* Timings derivation */
784 fclk_rate = clk_get_rate(master->fclk);
785 if (!fclk_rate)
786 return -EINVAL;
787
788 fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate);
789
790 /*
791 * Configure for Push-Pull mode.
792 */
793 if (master->scl_timing.i3c_pp_hi >= I3C_SCL_PP_PERIOD_NS_MIN &&
794 master->scl_timing.i3c_pp_lo >= master->scl_timing.i3c_pp_hi) {
795 ppbaud = DIV_ROUND_UP(master->scl_timing.i3c_pp_hi, fclk_period_ns) - 1;
796 if (ppbaud > NPCM_I3C_MAX_PPBAUD)
797 ppbaud = NPCM_I3C_MAX_PPBAUD;
798 pplow = DIV_ROUND_UP(master->scl_timing.i3c_pp_lo, fclk_period_ns)
799 - (ppbaud + 1);
800 if (pplow > NPCM_I3C_MAX_PPLOW)
801 pplow = NPCM_I3C_MAX_PPLOW;
802 bus->scl_rate.i3c = 1000000000 / (((ppbaud + 1) * 2 + pplow) * fclk_period_ns);
803 } else {
804 scl_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i3c);
805 if (bus->scl_rate.i3c == 10000000) {
806 /* Workaround for npcm8xx: 40/60 ns */
807 ppbaud = DIV_ROUND_UP(40, fclk_period_ns) - 1;
808 pplow = DIV_ROUND_UP(20, fclk_period_ns);
809 } else {
810 /* 50% duty-cycle */
811 ppbaud = DIV_ROUND_UP((scl_period_ns / 2), fclk_period_ns) - 1;
812 pplow = 0;
813 }
814 if (ppbaud > NPCM_I3C_MAX_PPBAUD)
815 ppbaud = NPCM_I3C_MAX_PPBAUD;
816 }
817 pp_high_period_ns = (ppbaud + 1) * fclk_period_ns;
818
819 /*
820 * Configure for Open-Drain mode.
821 */
822 if (master->scl_timing.i3c_od_hi >= pp_high_period_ns &&
823 master->scl_timing.i3c_od_lo >= I3C_SCL_OD_LOW_PERIOD_NS_MIN) {
824 if (master->scl_timing.i3c_od_hi == pp_high_period_ns)
825 odhpp = 1;
826 else
827 odhpp = 0;
828 odbaud = DIV_ROUND_UP(master->scl_timing.i3c_od_lo, pp_high_period_ns) - 1;
829 } else {
830 /* Set default OD timing: 1MHz/1000ns with 50% duty cycle */
831 odhpp = 0;
832 odbaud = DIV_ROUND_UP(500, pp_high_period_ns) - 1;
833 }
834 if (odbaud > NPCM_I3C_MAX_ODBAUD)
835 odbaud = NPCM_I3C_MAX_ODBAUD;
836 od_low_period_ns = (odbaud + 1) * pp_high_period_ns;
837
838 /* Configure for I2C mode */
839 i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c);
840 if (i2c_period_ns < od_low_period_ns * 2)
841 i2c_period_ns = od_low_period_ns * 2;
842 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2;
843 if (i2cbaud > NPCM_I3C_MAX_I2CBAUD)
844 i2cbaud = NPCM_I3C_MAX_I2CBAUD;
845
846 i3c_scl_rate = 1000000000 / (((ppbaud + 1) * 2 + pplow) * fclk_period_ns);
847 i2c_scl_rate = 1000000000 / ((i2cbaud + 2) * od_low_period_ns);
848
849 reg = NPCM_I3C_MCONFIG_MASTER_EN |
850 NPCM_I3C_MCONFIG_DISTO(0) |
851 NPCM_I3C_MCONFIG_HKEEP(3) |
852 NPCM_I3C_MCONFIG_ODSTOP(1) |
853 NPCM_I3C_MCONFIG_PPBAUD(ppbaud) |
854 NPCM_I3C_MCONFIG_PPLOW(pplow) |
855 NPCM_I3C_MCONFIG_ODBAUD(odbaud) |
856 NPCM_I3C_MCONFIG_ODHPP(odhpp) |
857 NPCM_I3C_MCONFIG_SKEW(0) |
858 NPCM_I3C_MCONFIG_I2CBAUD(i2cbaud);
859 writel(reg, master->regs + NPCM_I3C_MCONFIG);
860
861 dev_dbg(master->dev, "dts: i3c rate=%lu, i2c rate=%lu\n",
862 bus->scl_rate.i3c, bus->scl_rate.i2c);
863 dev_info(master->dev, "fclk=%lu, period_ns=%lu\n", fclk_rate, fclk_period_ns);
864 dev_info(master->dev, "i3c scl_rate=%lu\n", i3c_scl_rate);
865 dev_info(master->dev, "i2c scl_rate=%lu\n", i2c_scl_rate);
866 dev_info(master->dev, "pp_high=%u, pp_low=%lu\n", pp_high_period_ns,
867 (ppbaud + 1 + pplow) * fclk_period_ns);
868 dev_info(master->dev, "pp_sda_rd_skew=%d, pp_sda_wr_skew=%d\n",
869 master->scl_timing.i3c_pp_sda_rd_skew,
870 master->scl_timing.i3c_pp_sda_wr_skew);
871 dev_info(master->dev, "od_high=%d, od_low=%d\n",
872 odhpp ? pp_high_period_ns : od_low_period_ns, od_low_period_ns);
873 dev_dbg(master->dev, "i2c_high=%u, i2c_low=%u\n", ((i2cbaud >> 1) + 1) * od_low_period_ns,
874 ((i2cbaud >> 1) + 1 + (i2cbaud % 2)) * od_low_period_ns);
875 dev_dbg(master->dev, "ppbaud=%d, pplow=%d, odbaud=%d, i2cbaud=%d\n",
876 ppbaud, pplow, odbaud, i2cbaud);
877 dev_info(master->dev, "mconfig=0x%x\n", readl(master->regs + NPCM_I3C_MCONFIG));
878 /* Master core's registration */
879 ret = i3c_master_get_free_addr(m, 0);
880 if (ret < 0)
881 return ret;
882
883 info.dyn_addr = ret;
884 reg = readl(master->regs + NPCM_I3C_VENDORID);
> 885 info.pid = (NPCM_I3C_VENDORID_VID(reg) << 33) | readl(master->regs + NPCM_I3C_PARTNO);
886
887 writel(NPCM_MDYNADDR_VALID | NPCM_MDYNADDR_ADDR(info.dyn_addr),
888 master->regs + NPCM_I3C_MDYNADDR);
889
890 ret = i3c_master_set_info(&master->base, &info);
891
892 return ret;
893 }
894

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