From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18E28CE8D6F for ; Fri, 14 Nov 2025 18:14:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2bbjd5a4MZ8WB0M422B+TBh5jn45yxXFeknzE8TsMXE=; b=vKmADz4K7YqWsu XzYc+bAprR6ulbJolr2BZksfw0IILmdCVKaesjEFg34YbmrmEK1MmAlThIqJNgz/1s6qOFIUj+hob LGpnPGhXIQ3VzbF6l5GxQ5cO4/tFUSZXQejzFRX0AvyytUnuM70XbPOLuC0I7T8FtKq2AyWYwLewx hOGFbhUO1pZ2Xx0k0CGZqwu7BfRpAiuzsP40zkec4bbjMo6YRk0NU0Szh5iYlNzF6TSxP1UTUwlgt FufnSLx1EgPwM+037D3IYMe1hIz3uSCTCvy5EWr2Oy6UNglhFnIkys6nzyeLcAAZQe06rY7ni3fw7 uGYXEvPOB6z+X+/9AB0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vJyJk-0000000CwdL-3arU; Fri, 14 Nov 2025 18:14:40 +0000 Received: from mgamail.intel.com ([198.175.65.19]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vJyJi-0000000CwUD-3fKv for linux-i3c@lists.infradead.org; Fri, 14 Nov 2025 18:14:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763144079; x=1794680079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rxT5ztVjZszRtQWmbdg1IVsmcWcM7UtiQoFDSx5+8iI=; b=EucKaURkPUrgRLDN/i00nWSNqH8enpVGjAvk14c7x3jiTI2BUprQO01E DP35g6EcHtql5hUbwiji2x/kPIii6oHmUvLXZoJ0ITqUXtCNHW+zuKg5r +KKmo9QToxrpgZQW/5g9kjzyPN+T4s07StzwdxIg2sPsVcAFtU3zFWShz b40hjOrWm9C2e1KZLRBfttSjXr08YZEnklg0RP0PYVYzsxGAzYbxh3xNS UGefTjdMwysltCbuBeryRPuYtzCgbmO8/I7t9VusHDHx9Q7yeVPjIOj9E DItghcVsy0qj0cZkTkDrjH5TO7ZujAyFSJz+cIoDllJih2qPRRioeKPU9 g==; X-CSE-ConnectionGUID: om4mbceDTPaTZ5Lv/8bhEA== X-CSE-MsgGUID: zGmLp2wrQv+GO2B16Co7Zg== X-IronPort-AV: E=McAfee;i="6800,10657,11613"; a="65129495" X-IronPort-AV: E=Sophos;i="6.19,305,1754982000"; d="scan'208";a="65129495" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2025 10:14:28 -0800 X-CSE-ConnectionGUID: lFhF+h1KSridvF7EFrf8QQ== X-CSE-MsgGUID: aX9Lu/WtShiSR694tUna2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,305,1754982000"; d="scan'208";a="189669022" Received: from rvuia-mobl.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.231]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2025 10:14:27 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org Subject: [PATCH V2 12/13] i3c: mipi-i3c-hci-pci: Add LTR support for Intel controllers Date: Fri, 14 Nov 2025 20:13:55 +0200 Message-ID: <20251114181356.66515-13-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251114181356.66515-1-adrian.hunter@intel.com> References: <20251114181356.66515-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251114_101438_973413_FF7149BE X-CRM114-Status: GOOD ( 14.90 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org Add support for Latency Tolerance Reporting (LTR) for Intel controllers. Implement PM ->set_latency_tolerance() callback to set LTR register values. Also expose LTR register values via debugfs. Signed-off-by: Adrian Hunter --- Changes in V2: Make use of FIELD_PREP() Improve handling of values that exceed the maximum .../master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index 3f391b0854ae..2c827e877d29 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -7,12 +7,15 @@ * Author: Jarkko Nikula */ #include +#include +#include #include #include #include #include #include #include +#include struct mipi_i3c_hci_pci { struct pci_dev *pci; @@ -35,10 +38,122 @@ static DEFINE_IDA(mipi_i3c_hci_pci_ida); #define INTEL_RESETS_RESET_DONE BIT(1) #define INTEL_RESETS_TIMEOUT_US (10 * USEC_PER_MSEC) +#define INTEL_ACTIVELTR 0x0c +#define INTEL_IDLELTR 0x10 + +#define INTEL_LTR_REQ BIT(15) +#define INTEL_LTR_SCALE_MASK GENMASK(11, 10) +#define INTEL_LTR_SCALE_1US FIELD_PREP(INTEL_LTR_SCALE_MASK, 2) +#define INTEL_LTR_SCALE_32US FIELD_PREP(INTEL_LTR_SCALE_MASK, 3) +#define INTEL_LTR_VALUE_MASK GENMASK(9, 0) + struct intel_host { void __iomem *priv; + u32 active_ltr; + u32 idle_ltr; + struct dentry *debugfs_root; }; +static void intel_cache_ltr(struct intel_host *host) +{ + host->active_ltr = readl(host->priv + INTEL_ACTIVELTR); + host->idle_ltr = readl(host->priv + INTEL_IDLELTR); +} + +static void intel_ltr_set(struct device *dev, s32 val) +{ + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev); + struct intel_host *host = hci->private; + u32 ltr; + + /* + * Program latency tolerance (LTR) accordingly what has been asked + * by the PM QoS layer or disable it in case we were passed + * negative value or PM_QOS_LATENCY_ANY. + */ + ltr = readl(host->priv + INTEL_ACTIVELTR); + + if (val == PM_QOS_LATENCY_ANY || val < 0) { + ltr &= ~INTEL_LTR_REQ; + } else { + ltr |= INTEL_LTR_REQ; + ltr &= ~INTEL_LTR_SCALE_MASK; + ltr &= ~INTEL_LTR_VALUE_MASK; + + if (val > INTEL_LTR_VALUE_MASK) { + val >>= 5; + if (val > INTEL_LTR_VALUE_MASK) + val = INTEL_LTR_VALUE_MASK; + ltr |= INTEL_LTR_SCALE_32US | val; + } else { + ltr |= INTEL_LTR_SCALE_1US | val; + } + } + + if (ltr == host->active_ltr) + return; + + writel(ltr, host->priv + INTEL_ACTIVELTR); + writel(ltr, host->priv + INTEL_IDLELTR); + + /* Cache the values into intel_host structure */ + intel_cache_ltr(host); +} + +static void intel_ltr_expose(struct device *dev) +{ + dev->power.set_latency_tolerance = intel_ltr_set; + dev_pm_qos_expose_latency_tolerance(dev); +} + +static void intel_ltr_hide(struct device *dev) +{ + dev_pm_qos_hide_latency_tolerance(dev); + dev->power.set_latency_tolerance = NULL; +} + +static struct dentry *intel_actualize_debugfs_root(bool add) +{ + static struct dentry *debugfs_root; + static DEFINE_MUTEX(lock); + static int ref_cnt; + + guard(mutex)(&lock); + + ref_cnt += add ? 1 : -1; + + if (ref_cnt) { + if (IS_ERR_OR_NULL(debugfs_root)) + debugfs_root = debugfs_create_dir("intel_i3c", NULL); + } else { + debugfs_remove(debugfs_root); + debugfs_root = NULL; + } + + return debugfs_root; +} + +static void intel_add_debugfs(struct mipi_i3c_hci_pci *hci) +{ + struct dentry *debugfs_root = intel_actualize_debugfs_root(true); + struct dentry *dir = debugfs_create_dir(dev_name(&hci->pci->dev), debugfs_root); + struct intel_host *host = hci->private; + + intel_cache_ltr(host); + + host->debugfs_root = dir; + debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr); + debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr); +} + +static void intel_remove_debugfs(struct mipi_i3c_hci_pci *hci) +{ + struct intel_host *host = hci->private; + + debugfs_remove_recursive(host->debugfs_root); + intel_actualize_debugfs_root(false); +} + static void intel_reset(void __iomem *priv) { u32 reg; @@ -73,11 +188,21 @@ static int intel_i3c_init(struct mipi_i3c_hci_pci *hci) intel_reset(priv); + intel_ltr_expose(&hci->pci->dev); + intel_add_debugfs(hci); + return 0; } +static void intel_exit(struct mipi_i3c_hci_pci *hci) +{ + intel_remove_debugfs(hci); + intel_ltr_hide(&hci->pci->dev); +} + static const struct mipi_i3c_hci_pci_info intel_info = { .init = intel_i3c_init, + .exit = intel_exit, }; static int mipi_i3c_hci_pci_probe(struct pci_dev *pci, -- 2.51.0 -- linux-i3c mailing list linux-i3c@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-i3c