[PATCH V3 00/21] i3c: mipi-i3c-hci-pci: Add Runtime PM support

[PATCH V3 00/21] i3c: mipi-i3c-hci-pci: Add Runtime PM support

[Adrian Hunter]

Hi

Changes in V3:

    i3c: master: Update hot-join flag only on success
    i3c: mipi-i3c-hci: Manage DMA deallocation via devres action
    i3c: mipi-i3c-hci: Factor out software reset into helper
    i3c: mipi-i3c-hci: Factor out IO mode setting into helper
    i3c: mipi-i3c-hci: Factor out master dynamic address setting into helper
    i3c: master: Introduce optional Runtime PM support
    i3c: mipi-i3c-hci: Add optional Runtime PM support
    i3c: mipi-i3c-hci-pci: Add Runtime PM support
	Add Frank's Rev'd-by

    i3c: mipi-i3c-hci: Factor out core initialization into helper
	Move I/O mode setting if I/O mode already selected, to a
	separate patch

      i3c: mipi-i3c-hci: Allow core re-initialization for Runtime PM support
	New patch

Changes in V2:
    Notably 3 new patches to factor out more common code.  Otherwise:

    i3c: mipi-i3c-hci: Reset RING_OPERATION1 fields during init
    i3c: mipi-i3c-hci: Ensure proper bus clean-up
	Add Frank's Rev'd-by

    i3c: master: Update hot-join flag only on success
	Add Fixes tag

    i3c: master: Replace WARN_ON() with dev_err() in i3c_dev_free_ibi_locked()
    i3c: mipi-i3c-hci: Switch DAT bitmap allocation to devm_bitmap_zalloc()
	Add Frank's Rev'd-by

    i3c: mipi-i3c-hci: Switch PIO data allocation to devm_kzalloc()
	Remove 'use' from commit message
	Add Frank's Rev'd-by

    i3c: mipi-i3c-hci: Manage DMA deallocation via devres action
	Move hci_dma_free() below hci_dma_cleanup() to make patch look
	better to review.
	Frank suggested using devm_add_action_and_reset() but it doesn't
	work because the error path needs to call hci_dma_cleanup() before
	hci_dma_free.

    i3c: mipi-i3c-hci: Cache DAT in memory for Runtime PM restore
    i3c: mipi-i3c-hci: Introduce helper to restore DAT
    i3c: mipi-i3c-hci: Extract ring initialization from hci_dma_init()
    i3c: mipi-i3c-hci: Add DMA suspend and resume support
    i3c: mipi-i3c-hci: Refactor PIO register initialization
    i3c: mipi-i3c-hci: Add PIO suspend and resume support
	Add Frank's Rev'd-by

    i3c: mipi-i3c-hci: Factor out software reset into helper
	Add to the commit message a sentence about additional error message
	when a timeout happens

    i3c: mipi-i3c-hci: Factor out IO mode setting into helper
    i3c: mipi-i3c-hci: Factor out core initialization into helper
    i3c: mipi-i3c-hci: Factor out master dynamic address setting into helper
	New patches

    i3c: master: Introduce optional Runtime PM support
	None
	Frank suggested dispensing with rpm_allowed.  That would be OK for
	drivers that do not enable runtime PM, but the drivers that do
	enable runtime PM (i.e. dw-i3c-master.c	and svc-i3c-master.c) might
	be affected.  rpm_allowed can be removed when they are converted to
	the new approach.

    i3c: mipi-i3c-hci: Add optional Runtime PM support
	Use new i3c_hci_reset_and_init() and i3c_hci_set_master_dyn_addr()
	Use devm_pm_runtime_set_active_enabled() which allows
	i3c_hci_rpm_disable() to be dropped.
	SET_RUNTIME_PM_OPS -> RUNTIME_PM_OPS

    i3c: mipi-i3c-hci-pci: Add Runtime PM support
	None


This patch set adds Runtime PM support to mipi-i3c-hci and
mipi-i3c-hci-pci.

Notably, the master core is enhanced to optionally support
doing the RPM gets/puts needed to ensure a device is runtime
resumed for all bus operations.  That alleviates mipi-i3c-hci
from having to do it, and if the approach is accepted, would
allow other master drivers to drop their RPM gets/puts.

There are a number of small patches making various improvements
for things hit during development.  Plus a bunch of patches
preparing for the main changes which are covered in the last 3
patches.


Adrian Hunter (21):
      i3c: mipi-i3c-hci: Reset RING_OPERATION1 fields during init
      i3c: mipi-i3c-hci: Ensure proper bus clean-up
      i3c: master: Update hot-join flag only on success
      i3c: master: Replace WARN_ON() with dev_err() in i3c_dev_free_ibi_locked()
      i3c: mipi-i3c-hci: Switch DAT bitmap allocation to devm_bitmap_zalloc()
      i3c: mipi-i3c-hci: Switch PIO data allocation to devm_kzalloc()
      i3c: mipi-i3c-hci: Manage DMA deallocation via devres action
      i3c: mipi-i3c-hci: Cache DAT in memory for Runtime PM restore
      i3c: mipi-i3c-hci: Introduce helper to restore DAT
      i3c: mipi-i3c-hci: Extract ring initialization from hci_dma_init()
      i3c: mipi-i3c-hci: Add DMA suspend and resume support
      i3c: mipi-i3c-hci: Refactor PIO register initialization
      i3c: mipi-i3c-hci: Add PIO suspend and resume support
      i3c: mipi-i3c-hci: Factor out software reset into helper
      i3c: mipi-i3c-hci: Factor out IO mode setting into helper
      i3c: mipi-i3c-hci: Factor out core initialization into helper
      i3c: mipi-i3c-hci: Allow core re-initialization for Runtime PM support
      i3c: mipi-i3c-hci: Factor out master dynamic address setting into helper
      i3c: master: Introduce optional Runtime PM support
      i3c: mipi-i3c-hci: Add optional Runtime PM support
      i3c: mipi-i3c-hci-pci: Add Runtime PM support

 drivers/i3c/device.c                               |  46 ++-
 drivers/i3c/internals.h                            |   4 +
 drivers/i3c/master.c                               | 101 +++++-
 drivers/i3c/master/mipi-i3c-hci/core.c             | 344 +++++++++++++++------
 drivers/i3c/master/mipi-i3c-hci/dat.h              |   2 +-
 drivers/i3c/master/mipi-i3c-hci/dat_v1.c           |  45 ++-
 drivers/i3c/master/mipi-i3c-hci/dma.c              | 163 +++++++---
 drivers/i3c/master/mipi-i3c-hci/hci.h              |  12 +
 drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c |  17 +
 drivers/i3c/master/mipi-i3c-hci/pio.c              |  63 ++--
 include/linux/i3c/master.h                         |   4 +
 11 files changed, 613 insertions(+), 188 deletions(-)


Regards
Adrian

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[PATCH V3 01/21] i3c: mipi-i3c-hci: Reset RING_OPERATION1 fields during init

[Adrian Hunter]

The MIPI I3C HCI specification does not define reset values for
RING_OPERATION1 fields, and some controllers (e.g., Intel) do not clear
them during a software reset.  Ensure the ring pointers are explicitly
set to zero during bus initialization to avoid inconsistent state.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/dma.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c
index 0f6bbe184e85..5515ed740ca4 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dma.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dma.c
@@ -340,6 +340,14 @@ static int hci_dma_init(struct i3c_hci *hci)
 		rh_reg_write(INTR_SIGNAL_ENABLE, regval);
 
 ring_ready:
+		/*
+		 * The MIPI I3C HCI specification does not document reset values for
+		 * RING_OPERATION1 fields and some controllers (e.g. Intel controllers)
+		 * do not reset the values, so ensure the ring pointers are set to zero
+		 * here.
+		 */
+		rh_reg_write(RING_OPERATION1, 0);
+
 		rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE |
 					   RING_CTRL_RUN_STOP);
 	}
-- 
2.51.0


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[PATCH V3 02/21] i3c: mipi-i3c-hci: Ensure proper bus clean-up

[Adrian Hunter]

Wait for the bus to fully disable before proceeding, ensuring that no
operations are still in progress.  Synchronize the IRQ handler only after
interrupt signals have been disabled.  This approach also handles cases
where bus disable might fail, preventing race conditions and ensuring a
consistent shutdown sequence.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/core.c | 32 +++++++++++++++++++++++---
 drivers/i3c/master/mipi-i3c-hci/dma.c  |  7 ++++++
 drivers/i3c/master/mipi-i3c-hci/hci.h  |  1 +
 drivers/i3c/master/mipi-i3c-hci/pio.c  |  2 ++
 4 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 6da5daf18166..0d3ec674878d 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -151,13 +151,39 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m)
 	return 0;
 }
 
+/* Bus disable should never fail, so be generous with the timeout */
+#define BUS_DISABLE_TIMEOUT_US (500 * USEC_PER_MSEC)
+
+static int i3c_hci_bus_disable(struct i3c_hci *hci)
+{
+	u32 regval;
+	int ret;
+
+	reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
+
+	/* Ensure controller is disabled */
+	ret = readx_poll_timeout(reg_read, HC_CONTROL, regval,
+				 !(regval & HC_CONTROL_BUS_ENABLE), 0, BUS_DISABLE_TIMEOUT_US);
+	if (ret)
+		dev_err(&hci->master.dev, "%s: Failed to disable bus\n", __func__);
+
+	return ret;
+}
+
+void i3c_hci_sync_irq_inactive(struct i3c_hci *hci)
+{
+	struct platform_device *pdev = to_platform_device(hci->master.dev.parent);
+	int irq = platform_get_irq(pdev, 0);
+
+	reg_write(INTR_SIGNAL_ENABLE, 0x0);
+	synchronize_irq(irq);
+}
+
 static void i3c_hci_bus_cleanup(struct i3c_master_controller *m)
 {
 	struct i3c_hci *hci = to_i3c_hci(m);
-	struct platform_device *pdev = to_platform_device(m->dev.parent);
 
-	reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
-	synchronize_irq(platform_get_irq(pdev, 0));
+	i3c_hci_bus_disable(hci);
 	hci->io->cleanup(hci);
 	if (hci->cmd == &mipi_i3c_hci_cmd_v1)
 		mipi_i3c_hci_dat_v1.cleanup(hci);
diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c
index 5515ed740ca4..54849aa98fad 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dma.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dma.c
@@ -160,6 +160,13 @@ static void hci_dma_cleanup(struct i3c_hci *hci)
 
 		rh_reg_write(INTR_SIGNAL_ENABLE, 0);
 		rh_reg_write(RING_CONTROL, 0);
+	}
+
+	i3c_hci_sync_irq_inactive(hci);
+
+	for (i = 0; i < rings->total; i++) {
+		rh = &rings->headers[i];
+
 		rh_reg_write(CR_SETUP, 0);
 		rh_reg_write(IBI_SETUP, 0);
 
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index 3f88b67bc5cc..fd08b701d094 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -142,5 +142,6 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
 void amd_set_od_pp_timing(struct i3c_hci *hci);
 void amd_set_resp_buf_thld(struct i3c_hci *hci);
+void i3c_hci_sync_irq_inactive(struct i3c_hci *hci);
 
 #endif
diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index 109c6c5d83d6..90dca56fc0c5 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -211,6 +211,8 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
 
 	pio_reg_write(INTR_SIGNAL_ENABLE, 0x0);
 
+	i3c_hci_sync_irq_inactive(hci);
+
 	if (pio) {
 		dev_dbg(&hci->master.dev, "status = %#x/%#x",
 			pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
-- 
2.51.0


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[PATCH V3 03/21] i3c: master: Update hot-join flag only on success

[Adrian Hunter]

To prevent inconsistent state when an error occurs, ensure the hot-join
flag is updated only when enabling or disabling hot-join succeeds.

Fixes: 317bacf960a48 ("i3c: master: add enable(disable) hot join in sys entry")
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	Add Fixes tag


 drivers/i3c/master.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index 7f606c871648..e6384bffd4ae 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -618,7 +618,8 @@ static int i3c_set_hotjoin(struct i3c_master_controller *master, bool enable)
 	else
 		ret = master->ops->disable_hotjoin(master);
 
-	master->hotjoin = enable;
+	if (!ret)
+		master->hotjoin = enable;
 
 	i3c_bus_normaluse_unlock(&master->bus);
 
-- 
2.51.0


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[PATCH V3 04/21] i3c: master: Replace WARN_ON() with dev_err() in i3c_dev_free_ibi_locked()

[Adrian Hunter]

IBI disable failures are not indicative of a software bug, so using
WARN_ON() is not appropriate.  Replace these warnings with dev_err().

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index e6384bffd4ae..ff6cbc044787 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -3113,8 +3113,11 @@ void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev)
 	if (!dev->ibi)
 		return;
 
-	if (WARN_ON(dev->ibi->enabled))
-		WARN_ON(i3c_dev_disable_ibi_locked(dev));
+	if (dev->ibi->enabled) {
+		dev_err(&master->dev, "Freeing IBI that is still enabled\n");
+		if (i3c_dev_disable_ibi_locked(dev))
+			dev_err(&master->dev, "Failed to disable IBI before freeing\n");
+	}
 
 	master->ops->free_ibi(dev);
 
-- 
2.51.0


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[PATCH V3 05/21] i3c: mipi-i3c-hci: Switch DAT bitmap allocation to devm_bitmap_zalloc()

[Adrian Hunter]

The driver already uses managed resources, so convert the Device Address
Table (DAT) bitmap allocation to use devm_bitmap_zalloc().  Remove the
manual cleanup routine.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/core.c   |  2 --
 drivers/i3c/master/mipi-i3c-hci/dat.h    |  1 -
 drivers/i3c/master/mipi-i3c-hci/dat_v1.c | 11 +++--------
 3 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 0d3ec674878d..c4b249fde764 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -185,8 +185,6 @@ static void i3c_hci_bus_cleanup(struct i3c_master_controller *m)
 
 	i3c_hci_bus_disable(hci);
 	hci->io->cleanup(hci);
-	if (hci->cmd == &mipi_i3c_hci_cmd_v1)
-		mipi_i3c_hci_dat_v1.cleanup(hci);
 }
 
 void mipi_i3c_hci_resume(struct i3c_hci *hci)
diff --git a/drivers/i3c/master/mipi-i3c-hci/dat.h b/drivers/i3c/master/mipi-i3c-hci/dat.h
index 1f0f345c3daf..5277c65fc601 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dat.h
+++ b/drivers/i3c/master/mipi-i3c-hci/dat.h
@@ -17,7 +17,6 @@
 
 struct hci_dat_ops {
 	int (*init)(struct i3c_hci *hci);
-	void (*cleanup)(struct i3c_hci *hci);
 	int (*alloc_entry)(struct i3c_hci *hci);
 	void (*free_entry)(struct i3c_hci *hci, unsigned int dat_idx);
 	void (*set_dynamic_addr)(struct i3c_hci *hci, unsigned int dat_idx, u8 addr);
diff --git a/drivers/i3c/master/mipi-i3c-hci/dat_v1.c b/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
index cc5d2deb23ab..c60ef5d77ca3 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
@@ -55,8 +55,10 @@ static int hci_dat_v1_init(struct i3c_hci *hci)
 	}
 
 	if (!hci->DAT_data) {
+		struct device *dev = hci->master.dev.parent;
+
 		/* use a bitmap for faster free slot search */
-		hci->DAT_data = bitmap_zalloc(hci->DAT_entries, GFP_KERNEL);
+		hci->DAT_data = devm_bitmap_zalloc(dev, hci->DAT_entries, GFP_KERNEL);
 		if (!hci->DAT_data)
 			return -ENOMEM;
 
@@ -70,12 +72,6 @@ static int hci_dat_v1_init(struct i3c_hci *hci)
 	return 0;
 }
 
-static void hci_dat_v1_cleanup(struct i3c_hci *hci)
-{
-	bitmap_free(hci->DAT_data);
-	hci->DAT_data = NULL;
-}
-
 static int hci_dat_v1_alloc_entry(struct i3c_hci *hci)
 {
 	unsigned int dat_idx;
@@ -170,7 +166,6 @@ static int hci_dat_v1_get_index(struct i3c_hci *hci, u8 dev_addr)
 
 const struct hci_dat_ops mipi_i3c_hci_dat_v1 = {
 	.init			= hci_dat_v1_init,
-	.cleanup		= hci_dat_v1_cleanup,
 	.alloc_entry		= hci_dat_v1_alloc_entry,
 	.free_entry		= hci_dat_v1_free_entry,
 	.set_dynamic_addr	= hci_dat_v1_set_dynamic_addr,
-- 
2.51.0


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[PATCH V3 06/21] i3c: mipi-i3c-hci: Switch PIO data allocation to devm_kzalloc()

[Adrian Hunter]

The driver already uses managed resources, so convert the PIO data
structure allocation to devm_zalloc().  Remove the manual kfree().

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Remove 'use' from commit message
	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/pio.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index 90dca56fc0c5..3d633abf6099 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -140,7 +140,7 @@ static int hci_pio_init(struct i3c_hci *hci)
 	struct hci_pio_data *pio;
 	u32 val, size_val, rx_thresh, tx_thresh, ibi_val;
 
-	pio = kzalloc(sizeof(*pio), GFP_KERNEL);
+	pio = devm_kzalloc(hci->master.dev.parent, sizeof(*pio), GFP_KERNEL);
 	if (!pio)
 		return -ENOMEM;
 
@@ -220,8 +220,6 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
 		BUG_ON(pio->curr_rx);
 		BUG_ON(pio->curr_tx);
 		BUG_ON(pio->curr_resp);
-		kfree(pio);
-		hci->io_data = NULL;
 	}
 }
 
-- 
2.51.0


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[PATCH V3 07/21] i3c: mipi-i3c-hci: Manage DMA deallocation via devres action

[Adrian Hunter]

The driver already uses devres for resource management, but the standard
resource-managed DMA allocation helpers cannot be used because they assume
the DMA device matches the managed device.

To address this, factor out the deallocation logic from hci_dma_cleanup()
into a new helper, hci_dma_free(), and register it as a devres action.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	Move hci_dma_free() below hci_dma_cleanup() to make patch look
	better to review

	Frank suggested using devm_add_action_and_reset() but it doesn't
	work because the error path needs to call hci_dma_cleanup() before
	hci_dma_free


 drivers/i3c/master/mipi-i3c-hci/dma.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c
index 54849aa98fad..4999cf3d9674 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dma.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dma.c
@@ -169,6 +169,22 @@ static void hci_dma_cleanup(struct i3c_hci *hci)
 
 		rh_reg_write(CR_SETUP, 0);
 		rh_reg_write(IBI_SETUP, 0);
+	}
+
+	rhs_reg_write(CONTROL, 0);
+}
+
+static void hci_dma_free(void *data)
+{
+	struct i3c_hci *hci = data;
+	struct hci_rings_data *rings = hci->io_data;
+	struct hci_rh_data *rh;
+
+	if (!rings)
+		return;
+
+	for (int i = 0; i < rings->total; i++) {
+		rh = &rings->headers[i];
 
 		if (rh->xfer)
 			dma_free_coherent(rings->sysdev,
@@ -190,8 +206,6 @@ static void hci_dma_cleanup(struct i3c_hci *hci)
 		kfree(rh->ibi_data);
 	}
 
-	rhs_reg_write(CONTROL, 0);
-
 	kfree(rings);
 	hci->io_data = NULL;
 }
@@ -359,10 +373,15 @@ static int hci_dma_init(struct i3c_hci *hci)
 					   RING_CTRL_RUN_STOP);
 	}
 
+	ret = devm_add_action(hci->master.dev.parent, hci_dma_free, hci);
+	if (ret)
+		goto err_out;
+
 	return 0;
 
 err_out:
 	hci_dma_cleanup(hci);
+	hci_dma_free(hci);
 	return ret;
 }
 
-- 
2.51.0


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[PATCH V3 08/21] i3c: mipi-i3c-hci: Cache DAT in memory for Runtime PM restore

[Adrian Hunter]

Prepare for Runtime PM support, which requires restoring the Device Address
Table (DAT) registers after resume.  Maintain a copy of DAT in memory so it
can be reprogrammed when the controller is powered back up.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/dat_v1.c | 29 +++++++++++++++++++-----
 drivers/i3c/master/mipi-i3c-hci/hci.h    |  6 +++++
 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/dat_v1.c b/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
index c60ef5d77ca3..644ab939be1c 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
@@ -34,13 +34,26 @@
 /*	DAT_0_IBI_PAYLOAD		W0_BIT_(12) */
 #define DAT_0_STATIC_ADDRESS		W0_MASK(6, 0)
 
-#define dat_w0_read(i)		readl(hci->DAT_regs + (i) * 8)
-#define dat_w1_read(i)		readl(hci->DAT_regs + (i) * 8 + 4)
-#define dat_w0_write(i, v)	writel(v, hci->DAT_regs + (i) * 8)
-#define dat_w1_write(i, v)	writel(v, hci->DAT_regs + (i) * 8 + 4)
+#define dat_w0_read(i)		hci->DAT[i].w0
+#define dat_w1_read(i)		hci->DAT[i].w1
+#define dat_w0_write(i, v)	hci_dat_w0_write(hci, i, v)
+#define dat_w1_write(i, v)	hci_dat_w1_write(hci, i, v)
+
+static inline void hci_dat_w0_write(struct i3c_hci *hci, int i, u32 v)
+{
+	hci->DAT[i].w0 = v;
+	writel(v, hci->DAT_regs + i * 8);
+}
+
+static inline void hci_dat_w1_write(struct i3c_hci *hci, int i, u32 v)
+{
+	hci->DAT[i].w1 = v;
+	writel(v, hci->DAT_regs + i * 8 + 4);
+}
 
 static int hci_dat_v1_init(struct i3c_hci *hci)
 {
+	struct device *dev = hci->master.dev.parent;
 	unsigned int dat_idx;
 
 	if (!hci->DAT_regs) {
@@ -54,9 +67,13 @@ static int hci_dat_v1_init(struct i3c_hci *hci)
 		return -EOPNOTSUPP;
 	}
 
-	if (!hci->DAT_data) {
-		struct device *dev = hci->master.dev.parent;
+	if (!hci->DAT) {
+		hci->DAT = devm_kcalloc(dev, hci->DAT_entries, hci->DAT_entry_size, GFP_KERNEL);
+		if (!hci->DAT)
+			return -ENOMEM;
+	}
 
+	if (!hci->DAT_data) {
 		/* use a bitmap for faster free slot search */
 		hci->DAT_data = devm_bitmap_zalloc(dev, hci->DAT_entries, GFP_KERNEL);
 		if (!hci->DAT_data)
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index fd08b701d094..aa8a03594e64 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -31,6 +31,11 @@
 
 struct hci_cmd_ops;
 
+struct dat_words {
+	u32 w0;
+	u32 w1;
+};
+
 /* Our main structure */
 struct i3c_hci {
 	struct i3c_master_controller master;
@@ -51,6 +56,7 @@ struct i3c_hci {
 	unsigned int DAT_entries;
 	unsigned int DAT_entry_size;
 	void *DAT_data;
+	struct dat_words *DAT;
 	unsigned int DCT_entries;
 	unsigned int DCT_entry_size;
 	u8 version_major;
-- 
2.51.0


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[PATCH V3 09/21] i3c: mipi-i3c-hci: Introduce helper to restore DAT

[Adrian Hunter]

Add a dedicated function to restore the Device Address Table (DAT) in
preparation for Runtime PM support.  This will allow reprogramming the DAT
after the controller resumes from a low-power state.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/dat.h    | 1 +
 drivers/i3c/master/mipi-i3c-hci/dat_v1.c | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/dat.h b/drivers/i3c/master/mipi-i3c-hci/dat.h
index 5277c65fc601..6881f19da77f 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dat.h
+++ b/drivers/i3c/master/mipi-i3c-hci/dat.h
@@ -24,6 +24,7 @@ struct hci_dat_ops {
 	void (*set_flags)(struct i3c_hci *hci, unsigned int dat_idx, u32 w0, u32 w1);
 	void (*clear_flags)(struct i3c_hci *hci, unsigned int dat_idx, u32 w0, u32 w1);
 	int (*get_index)(struct i3c_hci *hci, u8 address);
+	void (*restore)(struct i3c_hci *hci);
 };
 
 extern const struct hci_dat_ops mipi_i3c_hci_dat_v1;
diff --git a/drivers/i3c/master/mipi-i3c-hci/dat_v1.c b/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
index 644ab939be1c..852966aa20d9 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dat_v1.c
@@ -181,6 +181,14 @@ static int hci_dat_v1_get_index(struct i3c_hci *hci, u8 dev_addr)
 	return -ENODEV;
 }
 
+static void hci_dat_v1_restore(struct i3c_hci *hci)
+{
+	for (int i = 0; i < hci->DAT_entries; i++) {
+		writel(hci->DAT[i].w0, hci->DAT_regs + i * 8);
+		writel(hci->DAT[i].w1, hci->DAT_regs + i * 8 + 4);
+	}
+}
+
 const struct hci_dat_ops mipi_i3c_hci_dat_v1 = {
 	.init			= hci_dat_v1_init,
 	.alloc_entry		= hci_dat_v1_alloc_entry,
@@ -190,4 +198,5 @@ const struct hci_dat_ops mipi_i3c_hci_dat_v1 = {
 	.set_flags		= hci_dat_v1_set_flags,
 	.clear_flags		= hci_dat_v1_clear_flags,
 	.get_index		= hci_dat_v1_get_index,
+	.restore		= hci_dat_v1_restore,
 };
-- 
2.51.0


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[PATCH V3 10/21] i3c: mipi-i3c-hci: Extract ring initialization from hci_dma_init()

[Adrian Hunter]

Split the ring setup logic out of hci_dma_init() into a new helper
hci_dma_init_rings().  This refactoring prepares for Runtime PM support
by allowing DMA rings to be reinitialized independently after resume.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/dma.c | 118 +++++++++++++++-----------
 1 file changed, 68 insertions(+), 50 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c
index 4999cf3d9674..9ed69da52977 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dma.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dma.c
@@ -210,6 +210,71 @@ static void hci_dma_free(void *data)
 	hci->io_data = NULL;
 }
 
+static void hci_dma_init_rh(struct i3c_hci *hci, struct hci_rh_data *rh, int i)
+{
+	u32 regval;
+
+	rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma));
+	rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma));
+	rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma));
+	rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma));
+
+	regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);
+	rh_reg_write(CR_SETUP, regval);
+
+	rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
+	rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY |
+					 INTR_TRANSFER_COMPLETION |
+					 INTR_RING_OP |
+					 INTR_TRANSFER_ERR |
+					 INTR_IBI_RING_FULL |
+					 INTR_TRANSFER_ABORT);
+
+	if (i >= IBI_RINGS)
+		goto ring_ready;
+
+	rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma));
+	rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma));
+	rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma));
+	rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma));
+
+	regval = FIELD_PREP(IBI_STATUS_RING_SIZE, rh->ibi_status_entries) |
+		 FIELD_PREP(IBI_DATA_CHUNK_SIZE, ilog2(rh->ibi_chunk_sz) - 2) |
+		 FIELD_PREP(IBI_DATA_CHUNK_COUNT, rh->ibi_chunks_total);
+	rh_reg_write(IBI_SETUP, regval);
+
+	regval = rh_reg_read(INTR_SIGNAL_ENABLE);
+	regval |= INTR_IBI_READY;
+	rh_reg_write(INTR_SIGNAL_ENABLE, regval);
+
+ring_ready:
+	/*
+	 * The MIPI I3C HCI specification does not document reset values for
+	 * RING_OPERATION1 fields and some controllers (e.g. Intel controllers)
+	 * do not reset the values, so ensure the ring pointers are set to zero
+	 * here.
+	 */
+	rh_reg_write(RING_OPERATION1, 0);
+
+	rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE);
+	rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP);
+
+	rh->done_ptr = 0;
+	rh->ibi_chunk_ptr = 0;
+}
+
+static void hci_dma_init_rings(struct i3c_hci *hci)
+{
+	struct hci_rings_data *rings = hci->io_data;
+	u32 regval;
+
+	regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total);
+	rhs_reg_write(CONTROL, regval);
+
+	for (int i = 0; i < rings->total; i++)
+		hci_dma_init_rh(hci, &rings->headers[i], i);
+}
+
 static int hci_dma_init(struct i3c_hci *hci)
 {
 	struct hci_rings_data *rings;
@@ -247,9 +312,6 @@ static int hci_dma_init(struct i3c_hci *hci)
 	rings->total = nr_rings;
 	rings->sysdev = sysdev;
 
-	regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total);
-	rhs_reg_write(CONTROL, regval);
-
 	for (i = 0; i < rings->total; i++) {
 		u32 offset = rhs_reg_read(RHn_OFFSET(i));
 
@@ -284,26 +346,10 @@ static int hci_dma_init(struct i3c_hci *hci)
 		if (!rh->xfer || !rh->resp || !rh->src_xfers)
 			goto err_out;
 
-		rh_reg_write(CMD_RING_BASE_LO, lower_32_bits(rh->xfer_dma));
-		rh_reg_write(CMD_RING_BASE_HI, upper_32_bits(rh->xfer_dma));
-		rh_reg_write(RESP_RING_BASE_LO, lower_32_bits(rh->resp_dma));
-		rh_reg_write(RESP_RING_BASE_HI, upper_32_bits(rh->resp_dma));
-
-		regval = FIELD_PREP(CR_RING_SIZE, rh->xfer_entries);
-		rh_reg_write(CR_SETUP, regval);
-
-		rh_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
-		rh_reg_write(INTR_SIGNAL_ENABLE, INTR_IBI_READY |
-						 INTR_TRANSFER_COMPLETION |
-						 INTR_RING_OP |
-						 INTR_TRANSFER_ERR |
-						 INTR_IBI_RING_FULL |
-						 INTR_TRANSFER_ABORT);
-
 		/* IBIs */
 
 		if (i >= IBI_RINGS)
-			goto ring_ready;
+			continue;
 
 		regval = rh_reg_read(IBI_SETUP);
 		rh->ibi_status_sz = FIELD_GET(IBI_STATUS_STRUCT_SIZE, regval);
@@ -342,45 +388,17 @@ static int hci_dma_init(struct i3c_hci *hci)
 			ret = -ENOMEM;
 			goto err_out;
 		}
-
-		rh_reg_write(IBI_STATUS_RING_BASE_LO, lower_32_bits(rh->ibi_status_dma));
-		rh_reg_write(IBI_STATUS_RING_BASE_HI, upper_32_bits(rh->ibi_status_dma));
-		rh_reg_write(IBI_DATA_RING_BASE_LO, lower_32_bits(rh->ibi_data_dma));
-		rh_reg_write(IBI_DATA_RING_BASE_HI, upper_32_bits(rh->ibi_data_dma));
-
-		regval = FIELD_PREP(IBI_STATUS_RING_SIZE,
-				    rh->ibi_status_entries) |
-			 FIELD_PREP(IBI_DATA_CHUNK_SIZE,
-				    ilog2(rh->ibi_chunk_sz) - 2) |
-			 FIELD_PREP(IBI_DATA_CHUNK_COUNT,
-				    rh->ibi_chunks_total);
-		rh_reg_write(IBI_SETUP, regval);
-
-		regval = rh_reg_read(INTR_SIGNAL_ENABLE);
-		regval |= INTR_IBI_READY;
-		rh_reg_write(INTR_SIGNAL_ENABLE, regval);
-
-ring_ready:
-		/*
-		 * The MIPI I3C HCI specification does not document reset values for
-		 * RING_OPERATION1 fields and some controllers (e.g. Intel controllers)
-		 * do not reset the values, so ensure the ring pointers are set to zero
-		 * here.
-		 */
-		rh_reg_write(RING_OPERATION1, 0);
-
-		rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE |
-					   RING_CTRL_RUN_STOP);
 	}
 
 	ret = devm_add_action(hci->master.dev.parent, hci_dma_free, hci);
 	if (ret)
 		goto err_out;
 
+	hci_dma_init_rings(hci);
+
 	return 0;
 
 err_out:
-	hci_dma_cleanup(hci);
 	hci_dma_free(hci);
 	return ret;
 }
-- 
2.51.0


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[PATCH V3 11/21] i3c: mipi-i3c-hci: Add DMA suspend and resume support

[Adrian Hunter]

Introduce helper functions to suspend and resume DMA operations.  These
are required to prepare for upcoming Runtime PM support, ensuring that
DMA state is properly managed during power transitions.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/dma.c | 25 +++++++++++++++++++++++++
 drivers/i3c/master/mipi-i3c-hci/hci.h |  2 ++
 2 files changed, 27 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c
index 9ed69da52977..2e5b4974d431 100644
--- a/drivers/i3c/master/mipi-i3c-hci/dma.c
+++ b/drivers/i3c/master/mipi-i3c-hci/dma.c
@@ -275,6 +275,29 @@ static void hci_dma_init_rings(struct i3c_hci *hci)
 		hci_dma_init_rh(hci, &rings->headers[i], i);
 }
 
+static void hci_dma_suspend(struct i3c_hci *hci)
+{
+	struct hci_rings_data *rings = hci->io_data;
+	int n = rings ? rings->total : 0;
+
+	for (int i = 0; i < n; i++) {
+		struct hci_rh_data *rh = &rings->headers[i];
+
+		rh_reg_write(INTR_SIGNAL_ENABLE, 0);
+		rh_reg_write(RING_CONTROL, 0);
+	}
+
+	i3c_hci_sync_irq_inactive(hci);
+}
+
+static void hci_dma_resume(struct i3c_hci *hci)
+{
+	struct hci_rings_data *rings = hci->io_data;
+
+	if (rings)
+		hci_dma_init_rings(hci);
+}
+
 static int hci_dma_init(struct i3c_hci *hci)
 {
 	struct hci_rings_data *rings;
@@ -865,4 +888,6 @@ const struct hci_io_ops mipi_i3c_hci_dma = {
 	.request_ibi		= hci_dma_request_ibi,
 	.free_ibi		= hci_dma_free_ibi,
 	.recycle_ibi_slot	= hci_dma_recycle_ibi_slot,
+	.suspend		= hci_dma_suspend,
+	.resume			= hci_dma_resume,
 };
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index aa8a03594e64..38f927685d3b 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -125,6 +125,8 @@ struct hci_io_ops {
 				struct i3c_ibi_slot *slot);
 	int (*init)(struct i3c_hci *hci);
 	void (*cleanup)(struct i3c_hci *hci);
+	void (*suspend)(struct i3c_hci *hci);
+	void (*resume)(struct i3c_hci *hci);
 };
 
 extern const struct hci_io_ops mipi_i3c_hci_pio;
-- 
2.51.0


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[PATCH V3 12/21] i3c: mipi-i3c-hci: Refactor PIO register initialization

[Adrian Hunter]

Move the PIO register setup logic out of hci_pio_init() into a new
helper, __hci_pio_init().  This refactoring prepares for Runtime PM
support by allowing PIO registers to be reinitialized independently
after resume.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/pio.c | 45 +++++++++++++++++----------
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index 3d633abf6099..52d9f01d9ca9 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -135,27 +135,14 @@ struct hci_pio_data {
 	u32 enabled_irqs;
 };
 
-static int hci_pio_init(struct i3c_hci *hci)
+static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 {
-	struct hci_pio_data *pio;
 	u32 val, size_val, rx_thresh, tx_thresh, ibi_val;
-
-	pio = devm_kzalloc(hci->master.dev.parent, sizeof(*pio), GFP_KERNEL);
-	if (!pio)
-		return -ENOMEM;
-
-	hci->io_data = pio;
-	spin_lock_init(&pio->lock);
+	struct hci_pio_data *pio = hci->io_data;
 
 	size_val = pio_reg_read(QUEUE_SIZE);
-	dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
-		FIELD_GET(CR_QUEUE_SIZE, size_val));
-	dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
-		4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
-	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
-		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
-	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
-		4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
+	if (size_val_ptr)
+		*size_val_ptr = size_val;
 
 	/*
 	 * Let's initialize data thresholds to half of the actual FIFO size.
@@ -201,6 +188,30 @@ static int hci_pio_init(struct i3c_hci *hci)
 
 	/* Always accept error interrupts (will be activated on first xfer) */
 	pio->enabled_irqs = STAT_ALL_ERRORS;
+}
+
+static int hci_pio_init(struct i3c_hci *hci)
+{
+	struct hci_pio_data *pio;
+	u32 size_val;
+
+	pio = devm_kzalloc(hci->master.dev.parent, sizeof(*pio), GFP_KERNEL);
+	if (!pio)
+		return -ENOMEM;
+
+	hci->io_data = pio;
+	spin_lock_init(&pio->lock);
+
+	__hci_pio_init(hci, &size_val);
+
+	dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
+		FIELD_GET(CR_QUEUE_SIZE, size_val));
+	dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
+		4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
+	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
+		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
+	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
+		4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
 
 	return 0;
 }
-- 
2.51.0


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[PATCH V3 13/21] i3c: mipi-i3c-hci: Add PIO suspend and resume support

[Adrian Hunter]

Introduce helper functions to suspend and resume PIO operations.  These
are required to prepare for upcoming Runtime PM support, ensuring that
PIO state is properly managed during power transitions.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	None

Changes in V2:

	Add Frank's Rev'd-by


 drivers/i3c/master/mipi-i3c-hci/pio.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index 52d9f01d9ca9..8e868e81acda 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -190,6 +190,18 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 	pio->enabled_irqs = STAT_ALL_ERRORS;
 }
 
+static void hci_pio_suspend(struct i3c_hci *hci)
+{
+	pio_reg_write(INTR_SIGNAL_ENABLE, 0);
+
+	i3c_hci_sync_irq_inactive(hci);
+}
+
+static void hci_pio_resume(struct i3c_hci *hci)
+{
+	__hci_pio_init(hci, NULL);
+}
+
 static int hci_pio_init(struct i3c_hci *hci)
 {
 	struct hci_pio_data *pio;
@@ -1059,4 +1071,6 @@ const struct hci_io_ops mipi_i3c_hci_pio = {
 	.request_ibi		= hci_pio_request_ibi,
 	.free_ibi		= hci_pio_free_ibi,
 	.recycle_ibi_slot	= hci_pio_recycle_ibi_slot,
+	.suspend		= hci_pio_suspend,
+	.resume			= hci_pio_resume,
 };
-- 
2.51.0


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[PATCH V3 14/21] i3c: mipi-i3c-hci: Factor out software reset into helper

[Adrian Hunter]

Prepare for future reuse of the reset sequence in other contexts, such as
power management.  Move the software reset logic from i3c_hci_init() into a
dedicated helper function, i3c_hci_software_reset().

Software reset should never fail.  Print an error message if it does.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	Add to the commit message a sentence about additional error message
	when a timeout happens


 drivers/i3c/master/mipi-i3c-hci/core.c | 41 ++++++++++++++++++--------
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index c4b249fde764..3b0609cb7da7 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -585,6 +585,34 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
 	return result;
 }
 
+static int i3c_hci_software_reset(struct i3c_hci *hci)
+{
+	u32 regval;
+	int ret;
+
+	/*
+	 * SOFT_RST must be clear before we write to it.
+	 * Then we must wait until it clears again.
+	 */
+	ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,
+				 !(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC);
+	if (ret) {
+		dev_err(&hci->master.dev, "%s: Software reset stuck\n", __func__);
+		return ret;
+	}
+
+	reg_write(RESET_CONTROL, SOFT_RST);
+
+	ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,
+				 !(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC);
+	if (ret) {
+		dev_err(&hci->master.dev, "%s: Software reset failed\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int i3c_hci_init(struct i3c_hci *hci)
 {
 	bool size_in_dwords, mode_selector;
@@ -654,18 +682,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	if (ret)
 		return ret;
 
-	/*
-	 * Now let's reset the hardware.
-	 * SOFT_RST must be clear before we write to it.
-	 * Then we must wait until it clears again.
-	 */
-	ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,
-				 !(regval & SOFT_RST), 1, 10000);
-	if (ret)
-		return -ENXIO;
-	reg_write(RESET_CONTROL, SOFT_RST);
-	ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,
-				 !(regval & SOFT_RST), 1, 10000);
+	ret = i3c_hci_software_reset(hci);
 	if (ret)
 		return -ENXIO;
 
-- 
2.51.0


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[PATCH V3 15/21] i3c: mipi-i3c-hci: Factor out IO mode setting into helper

[Adrian Hunter]

Prepare for future reuse.  Move the IO mode setting logic from
i3c_hci_init() into a dedicated helper function, i3c_hci_set_io_mode().

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	New patch


 drivers/i3c/master/mipi-i3c-hci/core.c | 45 ++++++++++++++++++--------
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 3b0609cb7da7..569c8584045a 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -613,9 +613,35 @@ static int i3c_hci_software_reset(struct i3c_hci *hci)
 	return 0;
 }
 
+static inline bool is_version_1_1_or_newer(struct i3c_hci *hci)
+{
+	return hci->version_major > 1 || (hci->version_major == 1 && hci->version_minor > 0);
+}
+
+static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma)
+{
+	bool pio_mode;
+
+	if (dma)
+		reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE);
+	else
+		reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE);
+
+	if (!is_version_1_1_or_newer(hci))
+		return 0;
+
+	pio_mode = reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE;
+	if ((dma && pio_mode) || (!dma && !pio_mode)) {
+		dev_err(&hci->master.dev, "%s mode is stuck\n", pio_mode ? "PIO" : "DMA");
+		return -EIO;
+	}
+
+	return 0;
+}
+
 static int i3c_hci_init(struct i3c_hci *hci)
 {
-	bool size_in_dwords, mode_selector;
+	bool size_in_dwords;
 	u32 regval, offset;
 	int ret;
 
@@ -732,20 +758,14 @@ static int i3c_hci_init(struct i3c_hci *hci)
 		return -EINVAL;
 	}
 
-	mode_selector = hci->version_major > 1 ||
-				(hci->version_major == 1 && hci->version_minor > 0);
-
 	/* Quirk for HCI_QUIRK_PIO_MODE on AMD platforms */
 	if (hci->quirks & HCI_QUIRK_PIO_MODE)
 		hci->RHS_regs = NULL;
 
 	/* Try activating DMA operations first */
 	if (hci->RHS_regs) {
-		reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE);
-		if (mode_selector && (reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) {
-			dev_err(&hci->master.dev, "PIO mode is stuck\n");
-			ret = -EIO;
-		} else {
+		ret = i3c_hci_set_io_mode(hci, true);
+		if (!ret) {
 			hci->io = &mipi_i3c_hci_dma;
 			dev_dbg(&hci->master.dev, "Using DMA\n");
 		}
@@ -753,11 +773,8 @@ static int i3c_hci_init(struct i3c_hci *hci)
 
 	/* If no DMA, try PIO */
 	if (!hci->io && hci->PIO_regs) {
-		reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE);
-		if (mode_selector && !(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) {
-			dev_err(&hci->master.dev, "DMA mode is stuck\n");
-			ret = -EIO;
-		} else {
+		ret = i3c_hci_set_io_mode(hci, false);
+		if (!ret) {
 			hci->io = &mipi_i3c_hci_pio;
 			dev_dbg(&hci->master.dev, "Using PIO\n");
 		}
-- 
2.51.0


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[PATCH V3 16/21] i3c: mipi-i3c-hci: Factor out core initialization into helper

[Adrian Hunter]

Prepare for future reuse.  Move core initialization logic from
i3c_hci_init() into a dedicated helper function,
i3c_hci_reset_and_init().

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---


Changes in V3:

	Move I/O mode setting if I/O mode already selected, to a
	separate patch

Changes in V2:

	New patch


 drivers/i3c/master/mipi-i3c-hci/core.c | 142 +++++++++++++------------
 1 file changed, 75 insertions(+), 67 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 569c8584045a..8b8e3952d41d 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -639,6 +639,80 @@ static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma)
 	return 0;
 }
 
+static int i3c_hci_reset_and_init(struct i3c_hci *hci)
+{
+	u32 regval;
+	int ret;
+
+	ret = i3c_hci_software_reset(hci);
+	if (ret)
+		return -ENXIO;
+
+	/* Disable all interrupts */
+	reg_write(INTR_SIGNAL_ENABLE, 0x0);
+	/*
+	 * Only allow bit 31:10 signal updates because
+	 * Bit 0:9 are reserved in IP version >= 0.8
+	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
+	 */
+	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
+
+	/* Make sure our data ordering fits the host's */
+	regval = reg_read(HC_CONTROL);
+	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
+		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
+			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
+			reg_write(HC_CONTROL, regval);
+			regval = reg_read(HC_CONTROL);
+			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
+				dev_err(&hci->master.dev, "cannot set BE mode\n");
+				return -EOPNOTSUPP;
+			}
+		}
+	} else {
+		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
+			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
+			reg_write(HC_CONTROL, regval);
+			regval = reg_read(HC_CONTROL);
+			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
+				dev_err(&hci->master.dev, "cannot clear BE mode\n");
+				return -EOPNOTSUPP;
+			}
+		}
+	}
+
+	/* Try activating DMA operations first */
+	if (hci->RHS_regs) {
+		ret = i3c_hci_set_io_mode(hci, true);
+		if (!ret) {
+			hci->io = &mipi_i3c_hci_dma;
+			dev_dbg(&hci->master.dev, "Using DMA\n");
+		}
+	}
+
+	/* If no DMA, try PIO */
+	if (!hci->io && hci->PIO_regs) {
+		ret = i3c_hci_set_io_mode(hci, false);
+		if (!ret) {
+			hci->io = &mipi_i3c_hci_pio;
+			dev_dbg(&hci->master.dev, "Using PIO\n");
+		}
+	}
+
+	if (!hci->io) {
+		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
+		ret = ret ?: -EINVAL;
+	}
+	if (ret)
+		return ret;
+
+	/* Configure OD and PP timings for AMD platforms */
+	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
+		amd_set_od_pp_timing(hci);
+
+	return 0;
+}
+
 static int i3c_hci_init(struct i3c_hci *hci)
 {
 	bool size_in_dwords;
@@ -708,43 +782,6 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	if (ret)
 		return ret;
 
-	ret = i3c_hci_software_reset(hci);
-	if (ret)
-		return -ENXIO;
-
-	/* Disable all interrupts */
-	reg_write(INTR_SIGNAL_ENABLE, 0x0);
-	/*
-	 * Only allow bit 31:10 signal updates because
-	 * Bit 0:9 are reserved in IP version >= 0.8
-	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
-	 */
-	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
-
-	/* Make sure our data ordering fits the host's */
-	regval = reg_read(HC_CONTROL);
-	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
-		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
-			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
-			reg_write(HC_CONTROL, regval);
-			regval = reg_read(HC_CONTROL);
-			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
-				dev_err(&hci->master.dev, "cannot set BE mode\n");
-				return -EOPNOTSUPP;
-			}
-		}
-	} else {
-		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
-			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
-			reg_write(HC_CONTROL, regval);
-			regval = reg_read(HC_CONTROL);
-			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
-				dev_err(&hci->master.dev, "cannot clear BE mode\n");
-				return -EOPNOTSUPP;
-			}
-		}
-	}
-
 	/* Select our command descriptor model */
 	switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) {
 	case 0:
@@ -762,36 +799,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	if (hci->quirks & HCI_QUIRK_PIO_MODE)
 		hci->RHS_regs = NULL;
 
-	/* Try activating DMA operations first */
-	if (hci->RHS_regs) {
-		ret = i3c_hci_set_io_mode(hci, true);
-		if (!ret) {
-			hci->io = &mipi_i3c_hci_dma;
-			dev_dbg(&hci->master.dev, "Using DMA\n");
-		}
-	}
-
-	/* If no DMA, try PIO */
-	if (!hci->io && hci->PIO_regs) {
-		ret = i3c_hci_set_io_mode(hci, false);
-		if (!ret) {
-			hci->io = &mipi_i3c_hci_pio;
-			dev_dbg(&hci->master.dev, "Using PIO\n");
-		}
-	}
-
-	if (!hci->io) {
-		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
-		if (!ret)
-			ret = -EINVAL;
-		return ret;
-	}
-
-	/* Configure OD and PP timings for AMD platforms */
-	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
-		amd_set_od_pp_timing(hci);
-
-	return 0;
+	return i3c_hci_reset_and_init(hci);
 }
 
 static int i3c_hci_probe(struct platform_device *pdev)
-- 
2.51.0


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[PATCH V3 17/21] i3c: mipi-i3c-hci: Allow core re-initialization for Runtime PM support

[Adrian Hunter]

Prepare i3c_hci_reset_and_init() to support runtime resume.  Update it to
handle the case where the I/O mode has already been selected.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---


Changes in V3

	New patch


 drivers/i3c/master/mipi-i3c-hci/core.c | 38 ++++++++++++++------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 8b8e3952d41d..fc0a47a36961 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -681,27 +681,31 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci)
 		}
 	}
 
-	/* Try activating DMA operations first */
-	if (hci->RHS_regs) {
-		ret = i3c_hci_set_io_mode(hci, true);
-		if (!ret) {
-			hci->io = &mipi_i3c_hci_dma;
-			dev_dbg(&hci->master.dev, "Using DMA\n");
+	if (hci->io) {
+		ret = i3c_hci_set_io_mode(hci, hci->io == &mipi_i3c_hci_dma);
+	} else {
+		/* Try activating DMA operations first */
+		if (hci->RHS_regs) {
+			ret = i3c_hci_set_io_mode(hci, true);
+			if (!ret) {
+				hci->io = &mipi_i3c_hci_dma;
+				dev_dbg(&hci->master.dev, "Using DMA\n");
+			}
 		}
-	}
 
-	/* If no DMA, try PIO */
-	if (!hci->io && hci->PIO_regs) {
-		ret = i3c_hci_set_io_mode(hci, false);
-		if (!ret) {
-			hci->io = &mipi_i3c_hci_pio;
-			dev_dbg(&hci->master.dev, "Using PIO\n");
+		/* If no DMA, try PIO */
+		if (!hci->io && hci->PIO_regs) {
+			ret = i3c_hci_set_io_mode(hci, false);
+			if (!ret) {
+				hci->io = &mipi_i3c_hci_pio;
+				dev_dbg(&hci->master.dev, "Using PIO\n");
+			}
 		}
-	}
 
-	if (!hci->io) {
-		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
-		ret = ret ?: -EINVAL;
+		if (!hci->io) {
+			dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
+			ret = ret ?: -EINVAL;
+		}
 	}
 	if (ret)
 		return ret;
-- 
2.51.0


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[PATCH V3 18/21] i3c: mipi-i3c-hci: Factor out master dynamic address setting into helper

[Adrian Hunter]

Prepare for future reuse.  Move master dynamic address setting logic from
i3c_hci_bus_init() into a dedicated helper function,
i3c_hci_set_master_dyn_addr().

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	New patch


 drivers/i3c/master/mipi-i3c-hci/core.c | 12 +++++++++---
 drivers/i3c/master/mipi-i3c-hci/hci.h  |  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index fc0a47a36961..ec5425f07635 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -114,6 +114,12 @@ static inline struct i3c_hci *to_i3c_hci(struct i3c_master_controller *m)
 	return container_of(m, struct i3c_hci, master);
 }
 
+static void i3c_hci_set_master_dyn_addr(struct i3c_hci *hci)
+{
+	reg_write(MASTER_DEVICE_ADDR,
+		  MASTER_DYNAMIC_ADDR(hci->dyn_addr) | MASTER_DYNAMIC_ADDR_VALID);
+}
+
 static int i3c_hci_bus_init(struct i3c_master_controller *m)
 {
 	struct i3c_hci *hci = to_i3c_hci(m);
@@ -129,10 +135,10 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m)
 	ret = i3c_master_get_free_addr(m, 0);
 	if (ret < 0)
 		return ret;
-	reg_write(MASTER_DEVICE_ADDR,
-		  MASTER_DYNAMIC_ADDR(ret) | MASTER_DYNAMIC_ADDR_VALID);
+	hci->dyn_addr = ret;
+	i3c_hci_set_master_dyn_addr(hci);
 	memset(&info, 0, sizeof(info));
-	info.dyn_addr = ret;
+	info.dyn_addr = hci->dyn_addr;
 	ret = i3c_master_set_info(m, &info);
 	if (ret)
 		return ret;
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index 38f927685d3b..ed89228ea971 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -62,6 +62,7 @@ struct i3c_hci {
 	u8 version_major;
 	u8 version_minor;
 	u8 revision;
+	u8 dyn_addr;
 	u32 vendor_mipi_id;
 	u32 vendor_version_id;
 	u32 vendor_product_id;
-- 
2.51.0


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[PATCH V3 19/21] i3c: master: Introduce optional Runtime PM support

[Adrian Hunter]

Master drivers currently manage Runtime PM individually, but all require
runtime resume for bus operations.  This can be centralized in common code.

Add optional Runtime PM support to ensure the parent device is runtime
resumed before bus operations and auto-suspended afterward.

Notably, do not call ->bus_cleanup() if runtime resume fails.  Master
drivers that opt-in to core runtime PM support must take that into account.

Also provide an option to allow IBIs and hot-joins while runtime suspended.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	None

	Frank suggested dispensing with rpm_allowed.  That would be OK for
	drivers that do not enable runtime PM, but the drivers that do
	enable runtime PM (i.e. dw-i3c-master.c	and svc-i3c-master.c) might
	be affected.  rpm_allowed can be removed when they are converted to
	the new approach.


 drivers/i3c/device.c       | 46 +++++++++++++++++--
 drivers/i3c/internals.h    |  4 ++
 drivers/i3c/master.c       | 93 +++++++++++++++++++++++++++++++++++---
 include/linux/i3c/master.h |  4 ++
 4 files changed, 138 insertions(+), 9 deletions(-)

diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
index 8a156f5ad692..101eaa77de68 100644
--- a/drivers/i3c/device.c
+++ b/drivers/i3c/device.c
@@ -46,10 +46,16 @@ int i3c_device_do_xfers(struct i3c_device *dev, struct i3c_xfer *xfers,
 			return -EINVAL;
 	}
 
+	ret = i3c_bus_rpm_get(dev->bus);
+	if (ret)
+		return ret;
+
 	i3c_bus_normaluse_lock(dev->bus);
 	ret = i3c_dev_do_xfers_locked(dev->desc, xfers, nxfers, mode);
 	i3c_bus_normaluse_unlock(dev->bus);
 
+	i3c_bus_rpm_put(dev->bus);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(i3c_device_do_xfers);
@@ -66,10 +72,16 @@ int i3c_device_do_setdasa(struct i3c_device *dev)
 {
 	int ret;
 
+	ret = i3c_bus_rpm_get(dev->bus);
+	if (ret)
+		return ret;
+
 	i3c_bus_normaluse_lock(dev->bus);
 	ret = i3c_dev_setdasa_locked(dev->desc);
 	i3c_bus_normaluse_unlock(dev->bus);
 
+	i3c_bus_rpm_put(dev->bus);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(i3c_device_do_setdasa);
@@ -106,16 +118,27 @@ EXPORT_SYMBOL_GPL(i3c_device_get_info);
  */
 int i3c_device_disable_ibi(struct i3c_device *dev)
 {
-	int ret = -ENOENT;
+	int ret;
+
+	if (i3c_bus_rpm_ibi_allowed(dev->bus)) {
+		ret = i3c_bus_rpm_get(dev->bus);
+		if (ret)
+			return ret;
+	}
 
 	i3c_bus_normaluse_lock(dev->bus);
 	if (dev->desc) {
 		mutex_lock(&dev->desc->ibi_lock);
 		ret = i3c_dev_disable_ibi_locked(dev->desc);
 		mutex_unlock(&dev->desc->ibi_lock);
+	} else {
+		ret = -ENOENT;
 	}
 	i3c_bus_normaluse_unlock(dev->bus);
 
+	if (!ret || i3c_bus_rpm_ibi_allowed(dev->bus))
+		i3c_bus_rpm_put(dev->bus);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(i3c_device_disable_ibi);
@@ -135,16 +158,25 @@ EXPORT_SYMBOL_GPL(i3c_device_disable_ibi);
  */
 int i3c_device_enable_ibi(struct i3c_device *dev)
 {
-	int ret = -ENOENT;
+	int ret;
+
+	ret = i3c_bus_rpm_get(dev->bus);
+	if (ret)
+		return ret;
 
 	i3c_bus_normaluse_lock(dev->bus);
 	if (dev->desc) {
 		mutex_lock(&dev->desc->ibi_lock);
 		ret = i3c_dev_enable_ibi_locked(dev->desc);
 		mutex_unlock(&dev->desc->ibi_lock);
+	} else {
+		ret = -ENOENT;
 	}
 	i3c_bus_normaluse_unlock(dev->bus);
 
+	if (ret || i3c_bus_rpm_ibi_allowed(dev->bus))
+		i3c_bus_rpm_put(dev->bus);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(i3c_device_enable_ibi);
@@ -163,19 +195,27 @@ EXPORT_SYMBOL_GPL(i3c_device_enable_ibi);
 int i3c_device_request_ibi(struct i3c_device *dev,
 			   const struct i3c_ibi_setup *req)
 {
-	int ret = -ENOENT;
+	int ret;
 
 	if (!req->handler || !req->num_slots)
 		return -EINVAL;
 
+	ret = i3c_bus_rpm_get(dev->bus);
+	if (ret)
+		return ret;
+
 	i3c_bus_normaluse_lock(dev->bus);
 	if (dev->desc) {
 		mutex_lock(&dev->desc->ibi_lock);
 		ret = i3c_dev_request_ibi_locked(dev->desc, req);
 		mutex_unlock(&dev->desc->ibi_lock);
+	} else {
+		ret = -ENOENT;
 	}
 	i3c_bus_normaluse_unlock(dev->bus);
 
+	i3c_bus_rpm_put(dev->bus);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(i3c_device_request_ibi);
diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h
index f609e5098137..0f1f3f766623 100644
--- a/drivers/i3c/internals.h
+++ b/drivers/i3c/internals.h
@@ -11,6 +11,10 @@
 #include <linux/i3c/master.h>
 #include <linux/io.h>
 
+int __must_check i3c_bus_rpm_get(struct i3c_bus *bus);
+void i3c_bus_rpm_put(struct i3c_bus *bus);
+bool i3c_bus_rpm_ibi_allowed(struct i3c_bus *bus);
+
 void i3c_bus_normaluse_lock(struct i3c_bus *bus);
 void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
 
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index ff6cbc044787..594d61edcef4 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -106,6 +106,38 @@ static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev)
 	return container_of(dev, struct i3c_master_controller, dev);
 }
 
+static int __must_check i3c_master_rpm_get(struct i3c_master_controller *master)
+{
+	int ret = master->rpm_allowed ? pm_runtime_resume_and_get(master->dev.parent) : 0;
+
+	if (ret < 0) {
+		dev_err(master->dev.parent, "runtime resume failed, error %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static void i3c_master_rpm_put(struct i3c_master_controller *master)
+{
+	if (master->rpm_allowed)
+		pm_runtime_put_autosuspend(master->dev.parent);
+}
+
+int i3c_bus_rpm_get(struct i3c_bus *bus)
+{
+	return i3c_master_rpm_get(i3c_bus_to_i3c_master(bus));
+}
+
+void i3c_bus_rpm_put(struct i3c_bus *bus)
+{
+	i3c_master_rpm_put(i3c_bus_to_i3c_master(bus));
+}
+
+bool i3c_bus_rpm_ibi_allowed(struct i3c_bus *bus)
+{
+	return i3c_bus_to_i3c_master(bus)->rpm_ibi_allowed;
+}
+
 static const struct device_type i3c_device_type;
 
 static struct i3c_bus *dev_to_i3cbus(struct device *dev)
@@ -611,6 +643,12 @@ static int i3c_set_hotjoin(struct i3c_master_controller *master, bool enable)
 	if (!master->ops->enable_hotjoin || !master->ops->disable_hotjoin)
 		return -EINVAL;
 
+	if (enable || master->rpm_ibi_allowed) {
+		ret = i3c_master_rpm_get(master);
+		if (ret)
+			return ret;
+	}
+
 	i3c_bus_normaluse_lock(&master->bus);
 
 	if (enable)
@@ -623,6 +661,9 @@ static int i3c_set_hotjoin(struct i3c_master_controller *master, bool enable)
 
 	i3c_bus_normaluse_unlock(&master->bus);
 
+	if ((enable && ret) || (!enable && !ret) || master->rpm_ibi_allowed)
+		i3c_master_rpm_put(master);
+
 	return ret;
 }
 
@@ -1712,18 +1753,23 @@ int i3c_master_do_daa(struct i3c_master_controller *master)
 {
 	int ret;
 
+	ret = i3c_master_rpm_get(master);
+	if (ret)
+		return ret;
+
 	i3c_bus_maintenance_lock(&master->bus);
 	ret = master->ops->do_daa(master);
 	i3c_bus_maintenance_unlock(&master->bus);
 
 	if (ret)
-		return ret;
+		goto out;
 
 	i3c_bus_normaluse_lock(&master->bus);
 	i3c_master_register_new_i3c_devs(master);
 	i3c_bus_normaluse_unlock(&master->bus);
-
-	return 0;
+out:
+	i3c_master_rpm_put(master);
+	return ret;
 }
 EXPORT_SYMBOL_GPL(i3c_master_do_daa);
 
@@ -2065,8 +2111,17 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
 
 static void i3c_master_bus_cleanup(struct i3c_master_controller *master)
 {
-	if (master->ops->bus_cleanup)
-		master->ops->bus_cleanup(master);
+	if (master->ops->bus_cleanup) {
+		int ret = i3c_master_rpm_get(master);
+
+		if (ret) {
+			dev_err(&master->dev,
+				"runtime resume error: master bus_cleanup() not done\n");
+		} else {
+			master->ops->bus_cleanup(master);
+			i3c_master_rpm_put(master);
+		}
+	}
 
 	i3c_master_detach_free_devs(master);
 }
@@ -2421,6 +2476,10 @@ static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
 			return -EOPNOTSUPP;
 	}
 
+	ret = i3c_master_rpm_get(master);
+	if (ret)
+		return ret;
+
 	i3c_bus_normaluse_lock(&master->bus);
 	dev = i3c_master_find_i2c_dev_by_addr(master, addr);
 	if (!dev)
@@ -2429,6 +2488,8 @@ static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
 		ret = master->ops->i2c_xfers(dev, xfers, nxfers);
 	i3c_bus_normaluse_unlock(&master->bus);
 
+	i3c_master_rpm_put(master);
+
 	return ret ? ret : nxfers;
 }
 
@@ -2531,6 +2592,10 @@ static int i3c_i2c_notifier_call(struct notifier_block *nb, unsigned long action
 
 	master = i2c_adapter_to_i3c_master(adap);
 
+	ret = i3c_master_rpm_get(master);
+	if (ret)
+		return ret;
+
 	i3c_bus_maintenance_lock(&master->bus);
 	switch (action) {
 	case BUS_NOTIFY_ADD_DEVICE:
@@ -2544,6 +2609,8 @@ static int i3c_i2c_notifier_call(struct notifier_block *nb, unsigned long action
 	}
 	i3c_bus_maintenance_unlock(&master->bus);
 
+	i3c_master_rpm_put(master);
+
 	return ret;
 }
 
@@ -2881,6 +2948,10 @@ int i3c_master_register(struct i3c_master_controller *master,
 	INIT_LIST_HEAD(&master->boardinfo.i2c);
 	INIT_LIST_HEAD(&master->boardinfo.i3c);
 
+	ret = i3c_master_rpm_get(master);
+	if (ret)
+		return ret;
+
 	device_initialize(&master->dev);
 	dev_set_name(&master->dev, "i3c-%d", i3cbus->id);
 
@@ -2960,6 +3031,8 @@ int i3c_master_register(struct i3c_master_controller *master,
 	i3c_master_register_new_i3c_devs(master);
 	i3c_bus_normaluse_unlock(&master->bus);
 
+	i3c_master_rpm_put(master);
+
 	return 0;
 
 err_del_dev:
@@ -2969,6 +3042,7 @@ int i3c_master_register(struct i3c_master_controller *master,
 	i3c_master_bus_cleanup(master);
 
 err_put_dev:
+	i3c_master_rpm_put(master);
 	put_device(&master->dev);
 
 	return ret;
@@ -3114,8 +3188,15 @@ void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev)
 		return;
 
 	if (dev->ibi->enabled) {
+		int ret;
+
 		dev_err(&master->dev, "Freeing IBI that is still enabled\n");
-		if (i3c_dev_disable_ibi_locked(dev))
+		ret = i3c_master_rpm_get(master);
+		if (!ret) {
+			ret = i3c_dev_disable_ibi_locked(dev);
+			i3c_master_rpm_put(master);
+		}
+		if (ret)
 			dev_err(&master->dev, "Failed to disable IBI before freeing\n");
 	}
 
diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
index 6225ad28f210..c1ec597f655c 100644
--- a/include/linux/i3c/master.h
+++ b/include/linux/i3c/master.h
@@ -504,6 +504,8 @@ struct i3c_master_controller_ops {
  * @secondary: true if the master is a secondary master
  * @init_done: true when the bus initialization is done
  * @hotjoin: true if the master support hotjoin
+ * @rpm_allowed: true if Runtime PM allowed
+ * @rpm_ibi_allowed: true if IBI and Hot-Join allowed while runtime suspended
  * @boardinfo.i3c: list of I3C  boardinfo objects
  * @boardinfo.i2c: list of I2C boardinfo objects
  * @boardinfo: board-level information attached to devices connected on the bus
@@ -527,6 +529,8 @@ struct i3c_master_controller {
 	unsigned int secondary : 1;
 	unsigned int init_done : 1;
 	unsigned int hotjoin: 1;
+	unsigned int rpm_allowed: 1;
+	unsigned int rpm_ibi_allowed: 1;
 	struct {
 		struct list_head i3c;
 		struct list_head i2c;
-- 
2.51.0


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[PATCH V3 20/21] i3c: mipi-i3c-hci: Add optional Runtime PM support

[Adrian Hunter]

Implement optional Runtime PM support for the MIPI I3C HCI driver.
Introduce runtime suspend and resume callbacks to manage bus state and
restore hardware configuration after resume.  Optionally enable autosuspend
with a default delay of 1 second, and add helper functions to control
Runtime PM during probe and remove.

Read quirks from i3c_hci_driver_ids[] and set new quirk
HCI_QUIRK_RPM_ALLOWED for intel-lpss-i3c devices to enable runtime PM for
them.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	Use new i3c_hci_reset_and_init() and i3c_hci_set_master_dyn_addr()
	Use devm_pm_runtime_set_active_enabled() which allows
	i3c_hci_rpm_disable() to be dropped.
	SET_RUNTIME_PM_OPS -> RUNTIME_PM_OPS


 drivers/i3c/master/mipi-i3c-hci/core.c | 76 ++++++++++++++++++++++++--
 drivers/i3c/master/mipi-i3c-hci/hci.h  |  2 +
 2 files changed, 72 insertions(+), 6 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index ec5425f07635..02c5a133e329 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/platform_data/mipi-i3c-hci.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 
 #include "hci.h"
 #include "ext_caps.h"
@@ -182,6 +183,7 @@ void i3c_hci_sync_irq_inactive(struct i3c_hci *hci)
 	int irq = platform_get_irq(pdev, 0);
 
 	reg_write(INTR_SIGNAL_ENABLE, 0x0);
+	hci->irq_inactive = true;
 	synchronize_irq(irq);
 }
 
@@ -564,6 +566,14 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
 	irqreturn_t result = IRQ_NONE;
 	u32 val;
 
+	/*
+	 * The IRQ can be shared, so the handler may be called when the IRQ is
+	 * due to a different device. That could happen when runtime suspended,
+	 * so exit immediately if IRQs are not expected for this device.
+	 */
+	if (hci->irq_inactive)
+		return IRQ_NONE;
+
 	val = reg_read(INTR_STATUS);
 	reg_write(INTR_STATUS, val);
 	dev_dbg(&hci->master.dev, "INTR_STATUS %#x", val);
@@ -723,6 +733,55 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci)
 	return 0;
 }
 
+static int i3c_hci_runtime_suspend(struct device *dev)
+{
+	struct i3c_hci *hci = dev_get_drvdata(dev);
+	int ret;
+
+	ret = i3c_hci_bus_disable(hci);
+	if (ret)
+		return ret;
+
+	hci->io->suspend(hci);
+
+	return 0;
+}
+
+static int i3c_hci_runtime_resume(struct device *dev)
+{
+	struct i3c_hci *hci = dev_get_drvdata(dev);
+	int ret;
+
+	ret = i3c_hci_reset_and_init(hci);
+	if (ret)
+		return -EIO;
+
+	i3c_hci_set_master_dyn_addr(hci);
+
+	mipi_i3c_hci_dat_v1.restore(hci);
+
+	hci->irq_inactive = false;
+
+	hci->io->resume(hci);
+
+	reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
+
+	return 0;
+}
+
+#define DEFAULT_AUTOSUSPEND_DELAY_MS 1000
+
+static void i3c_hci_rpm_enable(struct device *dev)
+{
+	struct i3c_hci *hci = dev_get_drvdata(dev);
+
+	pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY_MS);
+	pm_runtime_use_autosuspend(dev);
+	devm_pm_runtime_set_active_enabled(dev);
+
+	hci->master.rpm_allowed = true;
+}
+
 static int i3c_hci_init(struct i3c_hci *hci)
 {
 	bool size_in_dwords;
@@ -841,6 +900,8 @@ static int i3c_hci_probe(struct platform_device *pdev)
 	hci->master.dev.init_name = dev_name(&pdev->dev);
 
 	hci->quirks = (unsigned long)device_get_match_data(&pdev->dev);
+	if (!hci->quirks && platform_get_device_id(pdev))
+		hci->quirks = platform_get_device_id(pdev)->driver_data;
 
 	ret = i3c_hci_init(hci);
 	if (ret)
@@ -852,12 +913,10 @@ static int i3c_hci_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	ret = i3c_master_register(&hci->master, &pdev->dev,
-				  &i3c_hci_ops, false);
-	if (ret)
-		return ret;
+	if (hci->quirks & HCI_QUIRK_RPM_ALLOWED)
+		i3c_hci_rpm_enable(&pdev->dev);
 
-	return 0;
+	return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false);
 }
 
 static void i3c_hci_remove(struct platform_device *pdev)
@@ -880,11 +939,15 @@ static const struct acpi_device_id i3c_hci_acpi_match[] = {
 MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match);
 
 static const struct platform_device_id i3c_hci_driver_ids[] = {
-	{ .name = "intel-lpss-i3c" },
+	{ .name = "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
 
+static const struct dev_pm_ops i3c_hci_pm_ops = {
+	RUNTIME_PM_OPS(i3c_hci_runtime_suspend, i3c_hci_runtime_resume, NULL)
+};
+
 static struct platform_driver i3c_hci_driver = {
 	.probe = i3c_hci_probe,
 	.remove = i3c_hci_remove,
@@ -893,6 +956,7 @@ static struct platform_driver i3c_hci_driver = {
 		.name = "mipi-i3c-hci",
 		.of_match_table = of_match_ptr(i3c_hci_of_match),
 		.acpi_match_table = i3c_hci_acpi_match,
+		.pm = pm_ptr(&i3c_hci_pm_ops),
 	},
 };
 module_platform_driver(i3c_hci_driver);
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index ed89228ea971..6035f74212db 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -51,6 +51,7 @@ struct i3c_hci {
 	void *io_data;
 	const struct hci_cmd_ops *cmd;
 	atomic_t next_cmd_tid;
+	bool irq_inactive;
 	u32 caps;
 	unsigned int quirks;
 	unsigned int DAT_entries;
@@ -144,6 +145,7 @@ struct i3c_hci_dev_data {
 #define HCI_QUIRK_PIO_MODE	BIT(2)  /* Set PIO mode for AMD platforms */
 #define HCI_QUIRK_OD_PP_TIMING		BIT(3)  /* Set OD and PP timings for AMD platforms */
 #define HCI_QUIRK_RESP_BUF_THLD		BIT(4)  /* Set resp buf thld to 0 for AMD platforms */
+#define HCI_QUIRK_RPM_ALLOWED		BIT(5)  /* Runtime PM allowed */
 
 /* global functions */
 void mipi_i3c_hci_resume(struct i3c_hci *hci);
-- 
2.51.0


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[PATCH V3 21/21] i3c: mipi-i3c-hci-pci: Add Runtime PM support

[Adrian Hunter]

Enable Runtime PM for the mipi_i3c_hci_pci driver. Introduce helpers to
allow and forbid Runtime PM during probe and remove, using pm_runtime APIs.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---


Changes in V3:

	Add Frank's Rev'd-by

Changes in V2:

	None


 .../i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c  | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
index 458f871a2e61..1b38771667e5 100644
--- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
+++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
@@ -18,6 +18,7 @@
 #include <linux/platform_data/mipi-i3c-hci.h>
 #include <linux/platform_device.h>
 #include <linux/pm_qos.h>
+#include <linux/pm_runtime.h>
 
 /*
  * There can up to 15 instances, but implementations have at most 2 at this
@@ -208,6 +209,18 @@ static const struct mipi_i3c_hci_pci_info intel_si_2_info = {
 	.instance_count = 1,
 };
 
+static void mipi_i3c_hci_pci_rpm_allow(struct device *dev)
+{
+	pm_runtime_put(dev);
+	pm_runtime_allow(dev);
+}
+
+static void mipi_i3c_hci_pci_rpm_forbid(struct device *dev)
+{
+	pm_runtime_forbid(dev);
+	pm_runtime_get_sync(dev);
+}
+
 struct mipi_i3c_hci_pci_cell_data {
 	struct mipi_i3c_hci_platform_data pdata;
 	struct resource res;
@@ -285,6 +298,8 @@ static int mipi_i3c_hci_pci_probe(struct pci_dev *pci,
 
 	pci_set_drvdata(pci, hci);
 
+	mipi_i3c_hci_pci_rpm_allow(&pci->dev);
+
 	return 0;
 
 err_exit:
@@ -300,6 +315,8 @@ static void mipi_i3c_hci_pci_remove(struct pci_dev *pci)
 	if (hci->info->exit)
 		hci->info->exit(hci);
 
+	mipi_i3c_hci_pci_rpm_forbid(&pci->dev);
+
 	mfd_remove_devices(&pci->dev);
 }
 
-- 
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Re: [PATCH V3 16/21] i3c: mipi-i3c-hci: Factor out core initialization into helper

[Frank Li]

On Tue, Jan 13, 2026 at 09:26:57AM +0200, Adrian Hunter wrote:
> Prepare for future reuse.  Move core initialization logic from
> i3c_hci_init() into a dedicated helper function,
> i3c_hci_reset_and_init().
>
> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
>
>
> Changes in V3:
>
> 	Move I/O mode setting if I/O mode already selected, to a
> 	separate patch
>
> Changes in V2:
>
> 	New patch
>
>
>  drivers/i3c/master/mipi-i3c-hci/core.c | 142 +++++++++++++------------
>  1 file changed, 75 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index 569c8584045a..8b8e3952d41d 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -639,6 +639,80 @@ static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma)
>  	return 0;
>  }
>
> +static int i3c_hci_reset_and_init(struct i3c_hci *hci)
> +{
> +	u32 regval;
> +	int ret;
> +
> +	ret = i3c_hci_software_reset(hci);
> +	if (ret)
> +		return -ENXIO;
> +
> +	/* Disable all interrupts */
> +	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> +	/*
> +	 * Only allow bit 31:10 signal updates because
> +	 * Bit 0:9 are reserved in IP version >= 0.8
> +	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
> +	 */
> +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
> +
> +	/* Make sure our data ordering fits the host's */
> +	regval = reg_read(HC_CONTROL);
> +	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
> +		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> +			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
> +			reg_write(HC_CONTROL, regval);
> +			regval = reg_read(HC_CONTROL);
> +			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> +				dev_err(&hci->master.dev, "cannot set BE mode\n");
> +				return -EOPNOTSUPP;
> +			}
> +		}
> +	} else {
> +		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> +			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
> +			reg_write(HC_CONTROL, regval);
> +			regval = reg_read(HC_CONTROL);
> +			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> +				dev_err(&hci->master.dev, "cannot clear BE mode\n");
> +				return -EOPNOTSUPP;
> +			}
> +		}
> +	}
> +
> +	/* Try activating DMA operations first */
> +	if (hci->RHS_regs) {
> +		ret = i3c_hci_set_io_mode(hci, true);
> +		if (!ret) {
> +			hci->io = &mipi_i3c_hci_dma;
> +			dev_dbg(&hci->master.dev, "Using DMA\n");
> +		}
> +	}
> +
> +	/* If no DMA, try PIO */
> +	if (!hci->io && hci->PIO_regs) {
> +		ret = i3c_hci_set_io_mode(hci, false);
> +		if (!ret) {
> +			hci->io = &mipi_i3c_hci_pio;
> +			dev_dbg(&hci->master.dev, "Using PIO\n");
> +		}
> +	}
> +
> +	if (!hci->io) {
> +		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
> +		ret = ret ?: -EINVAL;
> +	}
> +	if (ret)
> +		return ret;
> +
> +	/* Configure OD and PP timings for AMD platforms */
> +	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
> +		amd_set_od_pp_timing(hci);
> +
> +	return 0;
> +}
> +
>  static int i3c_hci_init(struct i3c_hci *hci)
>  {
>  	bool size_in_dwords;
> @@ -708,43 +782,6 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	if (ret)
>  		return ret;
>
> -	ret = i3c_hci_software_reset(hci);
> -	if (ret)
> -		return -ENXIO;
> -
> -	/* Disable all interrupts */
> -	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> -	/*
> -	 * Only allow bit 31:10 signal updates because
> -	 * Bit 0:9 are reserved in IP version >= 0.8
> -	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
> -	 */
> -	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
> -
> -	/* Make sure our data ordering fits the host's */
> -	regval = reg_read(HC_CONTROL);
> -	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
> -		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> -			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
> -			reg_write(HC_CONTROL, regval);
> -			regval = reg_read(HC_CONTROL);
> -			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> -				dev_err(&hci->master.dev, "cannot set BE mode\n");
> -				return -EOPNOTSUPP;
> -			}
> -		}
> -	} else {
> -		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> -			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
> -			reg_write(HC_CONTROL, regval);
> -			regval = reg_read(HC_CONTROL);
> -			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> -				dev_err(&hci->master.dev, "cannot clear BE mode\n");
> -				return -EOPNOTSUPP;
> -			}
> -		}
> -	}
> -
>  	/* Select our command descriptor model */
>  	switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) {
>  	case 0:
> @@ -762,36 +799,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	if (hci->quirks & HCI_QUIRK_PIO_MODE)
>  		hci->RHS_regs = NULL;

these parts have not move into helper funciton.  Is it safe to use
"hci->RHS_regs" in helper funciton?

Frank

>
> -	/* Try activating DMA operations first */
> -	if (hci->RHS_regs) {
> -		ret = i3c_hci_set_io_mode(hci, true);
> -		if (!ret) {
> -			hci->io = &mipi_i3c_hci_dma;
> -			dev_dbg(&hci->master.dev, "Using DMA\n");
> -		}
> -	}
> -
> -	/* If no DMA, try PIO */
> -	if (!hci->io && hci->PIO_regs) {
> -		ret = i3c_hci_set_io_mode(hci, false);
> -		if (!ret) {
> -			hci->io = &mipi_i3c_hci_pio;
> -			dev_dbg(&hci->master.dev, "Using PIO\n");
> -		}
> -	}
> -
> -	if (!hci->io) {
> -		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
> -		if (!ret)
> -			ret = -EINVAL;
> -		return ret;
> -	}
> -
> -	/* Configure OD and PP timings for AMD platforms */
> -	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
> -		amd_set_od_pp_timing(hci);
> -
> -	return 0;
> +	return i3c_hci_reset_and_init(hci);
>  }
>
>  static int i3c_hci_probe(struct platform_device *pdev)
> --
> 2.51.0
>
>
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Re: [PATCH V3 17/21] i3c: mipi-i3c-hci: Allow core re-initialization for Runtime PM support

[Frank Li]

On Tue, Jan 13, 2026 at 09:26:58AM +0200, Adrian Hunter wrote:
> Prepare i3c_hci_reset_and_init() to support runtime resume.  Update it to
> handle the case where the I/O mode has already been selected.
>
> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
>
> Changes in V3
>
> 	New patch
>
>
>  drivers/i3c/master/mipi-i3c-hci/core.c | 38 ++++++++++++++------------
>  1 file changed, 21 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index 8b8e3952d41d..fc0a47a36961 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -681,27 +681,31 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci)
>  		}
>  	}
>
> -	/* Try activating DMA operations first */
> -	if (hci->RHS_regs) {
> -		ret = i3c_hci_set_io_mode(hci, true);
> -		if (!ret) {
> -			hci->io = &mipi_i3c_hci_dma;
> -			dev_dbg(&hci->master.dev, "Using DMA\n");
> +	if (hci->io) {
> +		ret = i3c_hci_set_io_mode(hci, hci->io == &mipi_i3c_hci_dma);
> +	} else {
> +		/* Try activating DMA operations first */
> +		if (hci->RHS_regs) {
> +			ret = i3c_hci_set_io_mode(hci, true);
> +			if (!ret) {
> +				hci->io = &mipi_i3c_hci_dma;
> +				dev_dbg(&hci->master.dev, "Using DMA\n");
> +			}
>  		}
> -	}
>
> -	/* If no DMA, try PIO */
> -	if (!hci->io && hci->PIO_regs) {
> -		ret = i3c_hci_set_io_mode(hci, false);
> -		if (!ret) {
> -			hci->io = &mipi_i3c_hci_pio;
> -			dev_dbg(&hci->master.dev, "Using PIO\n");
> +		/* If no DMA, try PIO */
> +		if (!hci->io && hci->PIO_regs) {
> +			ret = i3c_hci_set_io_mode(hci, false);
> +			if (!ret) {
> +				hci->io = &mipi_i3c_hci_pio;
> +				dev_dbg(&hci->master.dev, "Using PIO\n");
> +			}
>  		}
> -	}
>
> -	if (!hci->io) {
> -		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
> -		ret = ret ?: -EINVAL;
> +		if (!hci->io) {
> +			dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
> +			ret = ret ?: -EINVAL;
> +		}
>  	}
>  	if (ret)
>  		return ret;
> --
> 2.51.0
>
>
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Re: [PATCH V3 16/21] i3c: mipi-i3c-hci: Factor out core initialization into helper

[Adrian Hunter]

On 13/01/2026 18:27, Frank Li wrote:
> On Tue, Jan 13, 2026 at 09:26:57AM +0200, Adrian Hunter wrote:
>> Prepare for future reuse.  Move core initialization logic from
>> i3c_hci_init() into a dedicated helper function,
>> i3c_hci_reset_and_init().
>>
>> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
>> ---
>>
>>
>> Changes in V3:
>>
>> 	Move I/O mode setting if I/O mode already selected, to a
>> 	separate patch
>>
>> Changes in V2:
>>
>> 	New patch
>>
>>
>>  drivers/i3c/master/mipi-i3c-hci/core.c | 142 +++++++++++++------------
>>  1 file changed, 75 insertions(+), 67 deletions(-)
>>
>> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
>> index 569c8584045a..8b8e3952d41d 100644
>> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
>> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
>> @@ -639,6 +639,80 @@ static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma)
>>  	return 0;
>>  }
>>
>> +static int i3c_hci_reset_and_init(struct i3c_hci *hci)
>> +{
>> +	u32 regval;
>> +	int ret;
>> +
>> +	ret = i3c_hci_software_reset(hci);
>> +	if (ret)
>> +		return -ENXIO;
>> +
>> +	/* Disable all interrupts */
>> +	reg_write(INTR_SIGNAL_ENABLE, 0x0);
>> +	/*
>> +	 * Only allow bit 31:10 signal updates because
>> +	 * Bit 0:9 are reserved in IP version >= 0.8
>> +	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
>> +	 */
>> +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
>> +
>> +	/* Make sure our data ordering fits the host's */
>> +	regval = reg_read(HC_CONTROL);
>> +	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
>> +		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
>> +			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
>> +			reg_write(HC_CONTROL, regval);
>> +			regval = reg_read(HC_CONTROL);
>> +			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
>> +				dev_err(&hci->master.dev, "cannot set BE mode\n");
>> +				return -EOPNOTSUPP;
>> +			}
>> +		}
>> +	} else {
>> +		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
>> +			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
>> +			reg_write(HC_CONTROL, regval);
>> +			regval = reg_read(HC_CONTROL);
>> +			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
>> +				dev_err(&hci->master.dev, "cannot clear BE mode\n");
>> +				return -EOPNOTSUPP;
>> +			}
>> +		}
>> +	}
>> +
>> +	/* Try activating DMA operations first */
>> +	if (hci->RHS_regs) {
>> +		ret = i3c_hci_set_io_mode(hci, true);
>> +		if (!ret) {
>> +			hci->io = &mipi_i3c_hci_dma;
>> +			dev_dbg(&hci->master.dev, "Using DMA\n");
>> +		}
>> +	}
>> +
>> +	/* If no DMA, try PIO */
>> +	if (!hci->io && hci->PIO_regs) {
>> +		ret = i3c_hci_set_io_mode(hci, false);
>> +		if (!ret) {
>> +			hci->io = &mipi_i3c_hci_pio;
>> +			dev_dbg(&hci->master.dev, "Using PIO\n");
>> +		}
>> +	}
>> +
>> +	if (!hci->io) {
>> +		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
>> +		ret = ret ?: -EINVAL;
>> +	}
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Configure OD and PP timings for AMD platforms */
>> +	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
>> +		amd_set_od_pp_timing(hci);
>> +
>> +	return 0;
>> +}
>> +
>>  static int i3c_hci_init(struct i3c_hci *hci)
>>  {
>>  	bool size_in_dwords;
>> @@ -708,43 +782,6 @@ static int i3c_hci_init(struct i3c_hci *hci)
>>  	if (ret)
>>  		return ret;
>>
>> -	ret = i3c_hci_software_reset(hci);
>> -	if (ret)
>> -		return -ENXIO;
>> -
>> -	/* Disable all interrupts */
>> -	reg_write(INTR_SIGNAL_ENABLE, 0x0);
>> -	/*
>> -	 * Only allow bit 31:10 signal updates because
>> -	 * Bit 0:9 are reserved in IP version >= 0.8
>> -	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
>> -	 */
>> -	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
>> -
>> -	/* Make sure our data ordering fits the host's */
>> -	regval = reg_read(HC_CONTROL);
>> -	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
>> -		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
>> -			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
>> -			reg_write(HC_CONTROL, regval);
>> -			regval = reg_read(HC_CONTROL);
>> -			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
>> -				dev_err(&hci->master.dev, "cannot set BE mode\n");
>> -				return -EOPNOTSUPP;
>> -			}
>> -		}
>> -	} else {
>> -		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
>> -			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
>> -			reg_write(HC_CONTROL, regval);
>> -			regval = reg_read(HC_CONTROL);
>> -			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
>> -				dev_err(&hci->master.dev, "cannot clear BE mode\n");
>> -				return -EOPNOTSUPP;
>> -			}
>> -		}
>> -	}
>> -
>>  	/* Select our command descriptor model */
>>  	switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) {
>>  	case 0:
>> @@ -762,36 +799,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>>  	if (hci->quirks & HCI_QUIRK_PIO_MODE)
>>  		hci->RHS_regs = NULL;
> 
> these parts have not move into helper funciton.  Is it safe to use
> "hci->RHS_regs" in helper funciton?

These parts are initializing things that never need to be
re-initialized.

RHS_regs is the MMIO address of the Ring Headers section
for DMA, if there is one.  It is normally setup only once and
never changed, but the quirk above sets it to zero to prevent
DMA from being used.

The I/O mode (DMA or PIO) is selected during probe and never
changed.

> 
> Frank
> 
>>
>> -	/* Try activating DMA operations first */
>> -	if (hci->RHS_regs) {
>> -		ret = i3c_hci_set_io_mode(hci, true);
>> -		if (!ret) {
>> -			hci->io = &mipi_i3c_hci_dma;
>> -			dev_dbg(&hci->master.dev, "Using DMA\n");
>> -		}
>> -	}
>> -
>> -	/* If no DMA, try PIO */
>> -	if (!hci->io && hci->PIO_regs) {
>> -		ret = i3c_hci_set_io_mode(hci, false);
>> -		if (!ret) {
>> -			hci->io = &mipi_i3c_hci_pio;
>> -			dev_dbg(&hci->master.dev, "Using PIO\n");
>> -		}
>> -	}
>> -
>> -	if (!hci->io) {
>> -		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
>> -		if (!ret)
>> -			ret = -EINVAL;
>> -		return ret;
>> -	}
>> -
>> -	/* Configure OD and PP timings for AMD platforms */
>> -	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
>> -		amd_set_od_pp_timing(hci);
>> -
>> -	return 0;
>> +	return i3c_hci_reset_and_init(hci);
>>  }
>>
>>  static int i3c_hci_probe(struct platform_device *pdev)
>> --
>> 2.51.0
>>
>>
>> --
>> linux-i3c mailing list
>> linux-i3c@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-i3c


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Re: [PATCH V3 16/21] i3c: mipi-i3c-hci: Factor out core initialization into helper

[Frank Li]

On Tue, Jan 13, 2026 at 07:27:05PM +0200, Adrian Hunter wrote:
> On 13/01/2026 18:27, Frank Li wrote:
> > On Tue, Jan 13, 2026 at 09:26:57AM +0200, Adrian Hunter wrote:
> >> Prepare for future reuse.  Move core initialization logic from
> >> i3c_hci_init() into a dedicated helper function,
> >> i3c_hci_reset_and_init().
> >>
> >> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
> >> ---
> >>
> >>
> >> Changes in V3:
> >>
> >> 	Move I/O mode setting if I/O mode already selected, to a
> >> 	separate patch
> >>
> >> Changes in V2:
> >>
> >> 	New patch
> >>
> >>
> >>  drivers/i3c/master/mipi-i3c-hci/core.c | 142 +++++++++++++------------
> >>  1 file changed, 75 insertions(+), 67 deletions(-)
> >>
> >> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> >> index 569c8584045a..8b8e3952d41d 100644
> >> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> >> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> >> @@ -639,6 +639,80 @@ static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma)
> >>  	return 0;
> >>  }
> >>
> >> +static int i3c_hci_reset_and_init(struct i3c_hci *hci)
> >> +{
> >> +	u32 regval;
> >> +	int ret;
> >> +
> >> +	ret = i3c_hci_software_reset(hci);
> >> +	if (ret)
> >> +		return -ENXIO;
> >> +
> >> +	/* Disable all interrupts */
> >> +	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> >> +	/*
> >> +	 * Only allow bit 31:10 signal updates because
> >> +	 * Bit 0:9 are reserved in IP version >= 0.8
> >> +	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
> >> +	 */
> >> +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
> >> +
> >> +	/* Make sure our data ordering fits the host's */
> >> +	regval = reg_read(HC_CONTROL);
> >> +	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
> >> +		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> >> +			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
> >> +			reg_write(HC_CONTROL, regval);
> >> +			regval = reg_read(HC_CONTROL);
> >> +			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> >> +				dev_err(&hci->master.dev, "cannot set BE mode\n");
> >> +				return -EOPNOTSUPP;
> >> +			}
> >> +		}
> >> +	} else {
> >> +		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> >> +			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
> >> +			reg_write(HC_CONTROL, regval);
> >> +			regval = reg_read(HC_CONTROL);
> >> +			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> >> +				dev_err(&hci->master.dev, "cannot clear BE mode\n");
> >> +				return -EOPNOTSUPP;
> >> +			}
> >> +		}
> >> +	}
> >> +
> >> +	/* Try activating DMA operations first */
> >> +	if (hci->RHS_regs) {
> >> +		ret = i3c_hci_set_io_mode(hci, true);
> >> +		if (!ret) {
> >> +			hci->io = &mipi_i3c_hci_dma;
> >> +			dev_dbg(&hci->master.dev, "Using DMA\n");
> >> +		}
> >> +	}
> >> +
> >> +	/* If no DMA, try PIO */
> >> +	if (!hci->io && hci->PIO_regs) {
> >> +		ret = i3c_hci_set_io_mode(hci, false);
> >> +		if (!ret) {
> >> +			hci->io = &mipi_i3c_hci_pio;
> >> +			dev_dbg(&hci->master.dev, "Using PIO\n");
> >> +		}
> >> +	}
> >> +
> >> +	if (!hci->io) {
> >> +		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
> >> +		ret = ret ?: -EINVAL;
> >> +	}
> >> +	if (ret)
> >> +		return ret;
> >> +
> >> +	/* Configure OD and PP timings for AMD platforms */
> >> +	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
> >> +		amd_set_od_pp_timing(hci);
> >> +
> >> +	return 0;
> >> +}
> >> +
> >>  static int i3c_hci_init(struct i3c_hci *hci)
> >>  {
> >>  	bool size_in_dwords;
> >> @@ -708,43 +782,6 @@ static int i3c_hci_init(struct i3c_hci *hci)
> >>  	if (ret)
> >>  		return ret;
> >>
> >> -	ret = i3c_hci_software_reset(hci);
> >> -	if (ret)
> >> -		return -ENXIO;
> >> -
> >> -	/* Disable all interrupts */
> >> -	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> >> -	/*
> >> -	 * Only allow bit 31:10 signal updates because
> >> -	 * Bit 0:9 are reserved in IP version >= 0.8
> >> -	 * Bit 0:5 are defined in IP version < 0.8 but not handled by PIO code
> >> -	 */
> >> -	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
> >> -
> >> -	/* Make sure our data ordering fits the host's */
> >> -	regval = reg_read(HC_CONTROL);
> >> -	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
> >> -		if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> >> -			regval |= HC_CONTROL_DATA_BIG_ENDIAN;
> >> -			reg_write(HC_CONTROL, regval);
> >> -			regval = reg_read(HC_CONTROL);
> >> -			if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
> >> -				dev_err(&hci->master.dev, "cannot set BE mode\n");
> >> -				return -EOPNOTSUPP;
> >> -			}
> >> -		}
> >> -	} else {
> >> -		if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> >> -			regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
> >> -			reg_write(HC_CONTROL, regval);
> >> -			regval = reg_read(HC_CONTROL);
> >> -			if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
> >> -				dev_err(&hci->master.dev, "cannot clear BE mode\n");
> >> -				return -EOPNOTSUPP;
> >> -			}
> >> -		}
> >> -	}
> >> -
> >>  	/* Select our command descriptor model */
> >>  	switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) {
> >>  	case 0:
> >> @@ -762,36 +799,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
> >>  	if (hci->quirks & HCI_QUIRK_PIO_MODE)
> >>  		hci->RHS_regs = NULL;
> >
> > these parts have not move into helper funciton.  Is it safe to use
> > "hci->RHS_regs" in helper funciton?
>
> These parts are initializing things that never need to be
> re-initialized.
>
> RHS_regs is the MMIO address of the Ring Headers section
> for DMA, if there is one.  It is normally setup only once and
> never changed, but the quirk above sets it to zero to prevent
> DMA from being used.
>
> The I/O mode (DMA or PIO) is selected during probe and never
> changed.

Okay
Reviewed-by: Frank Li <Frank.Li@nxp.com>

>
> >
> > Frank
> >
> >>
> >> -	/* Try activating DMA operations first */
> >> -	if (hci->RHS_regs) {
> >> -		ret = i3c_hci_set_io_mode(hci, true);
> >> -		if (!ret) {
> >> -			hci->io = &mipi_i3c_hci_dma;
> >> -			dev_dbg(&hci->master.dev, "Using DMA\n");
> >> -		}
> >> -	}
> >> -
> >> -	/* If no DMA, try PIO */
> >> -	if (!hci->io && hci->PIO_regs) {
> >> -		ret = i3c_hci_set_io_mode(hci, false);
> >> -		if (!ret) {
> >> -			hci->io = &mipi_i3c_hci_pio;
> >> -			dev_dbg(&hci->master.dev, "Using PIO\n");
> >> -		}
> >> -	}
> >> -
> >> -	if (!hci->io) {
> >> -		dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
> >> -		if (!ret)
> >> -			ret = -EINVAL;
> >> -		return ret;
> >> -	}
> >> -
> >> -	/* Configure OD and PP timings for AMD platforms */
> >> -	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
> >> -		amd_set_od_pp_timing(hci);
> >> -
> >> -	return 0;
> >> +	return i3c_hci_reset_and_init(hci);
> >>  }
> >>
> >>  static int i3c_hci_probe(struct platform_device *pdev)
> >> --
> >> 2.51.0
> >>
> >>
> >> --
> >> linux-i3c mailing list
> >> linux-i3c@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-i3c
>
>
> --
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> http://lists.infradead.org/mailman/listinfo/linux-i3c

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Re: [PATCH V3 00/21] i3c: mipi-i3c-hci-pci: Add Runtime PM support

[Alexandre Belloni]

On Tue, 13 Jan 2026 09:26:41 +0200, Adrian Hunter wrote:
> Changes in V3:
> 
>     i3c: master: Update hot-join flag only on success
>     i3c: mipi-i3c-hci: Manage DMA deallocation via devres action
>     i3c: mipi-i3c-hci: Factor out software reset into helper
>     i3c: mipi-i3c-hci: Factor out IO mode setting into helper
>     i3c: mipi-i3c-hci: Factor out master dynamic address setting into helper
>     i3c: master: Introduce optional Runtime PM support
>     i3c: mipi-i3c-hci: Add optional Runtime PM support
>     i3c: mipi-i3c-hci-pci: Add Runtime PM support
> 	Add Frank's Rev'd-by
> 
> [...]

Applied, thanks!

[01/21] i3c: mipi-i3c-hci: Reset RING_OPERATION1 fields during init
        https://git.kernel.org/i3c/c/78f63ae4a82d
[02/21] i3c: mipi-i3c-hci: Ensure proper bus clean-up
        https://git.kernel.org/i3c/c/8bb96575883d
[03/21] i3c: master: Update hot-join flag only on success
        https://git.kernel.org/i3c/c/f0775157b9f9
[04/21] i3c: master: Replace WARN_ON() with dev_err() in i3c_dev_free_ibi_locked()
        https://git.kernel.org/i3c/c/471895799c2f
[05/21] i3c: mipi-i3c-hci: Switch DAT bitmap allocation to devm_bitmap_zalloc()
        https://git.kernel.org/i3c/c/f64c1a46ea7c
[06/21] i3c: mipi-i3c-hci: Switch PIO data allocation to devm_kzalloc()
        https://git.kernel.org/i3c/c/11d17c2855bf
[07/21] i3c: mipi-i3c-hci: Manage DMA deallocation via devres action
        https://git.kernel.org/i3c/c/29bf98a6346a
[08/21] i3c: mipi-i3c-hci: Cache DAT in memory for Runtime PM restore
        https://git.kernel.org/i3c/c/a372cfac056a
[09/21] i3c: mipi-i3c-hci: Introduce helper to restore DAT
        https://git.kernel.org/i3c/c/f180524a4877
[10/21] i3c: mipi-i3c-hci: Extract ring initialization from hci_dma_init()
        https://git.kernel.org/i3c/c/f5401c973e7f
[11/21] i3c: mipi-i3c-hci: Add DMA suspend and resume support
        https://git.kernel.org/i3c/c/816958720443
[12/21] i3c: mipi-i3c-hci: Refactor PIO register initialization
        https://git.kernel.org/i3c/c/ca4d4682d353
[13/21] i3c: mipi-i3c-hci: Add PIO suspend and resume support
        https://git.kernel.org/i3c/c/8afa0dd83b60
[14/21] i3c: mipi-i3c-hci: Factor out software reset into helper
        https://git.kernel.org/i3c/c/57a2f976ac18
[15/21] i3c: mipi-i3c-hci: Factor out IO mode setting into helper
        https://git.kernel.org/i3c/c/e4269df518d6
[16/21] i3c: mipi-i3c-hci: Factor out core initialization into helper
        https://git.kernel.org/i3c/c/7f91e0e6aa3f
[17/21] i3c: mipi-i3c-hci: Allow core re-initialization for Runtime PM support
        https://git.kernel.org/i3c/c/f2b5d43c93e0
[18/21] i3c: mipi-i3c-hci: Factor out master dynamic address setting into helper
        https://git.kernel.org/i3c/c/3c3de6803a7d
[19/21] i3c: master: Introduce optional Runtime PM support
        https://git.kernel.org/i3c/c/990c149c61ee
[20/21] i3c: mipi-i3c-hci: Add optional Runtime PM support
        https://git.kernel.org/i3c/c/b9a15012a145
[21/21] i3c: mipi-i3c-hci-pci: Add Runtime PM support
        https://git.kernel.org/i3c/c/95cb1935168a

Best regards,

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