[PATCH v2 0/5] Introduce initial AMD I3C HCI driver support

Shyam Sundar S K
2024-07-24T07:13:31Z

The AMD SoC includes an I3C IP block as part of the Fusion Controller Hub
(FCH). This series introduces the initial driver support to enable the I3C
IP block on AMD's latest processors.

Currently, the code is closely tied to dt-bindings. This initial set aims
to decouple some of these bindings by adding the MIPI ID, allowing the
current driver to support ACPI-enabled x86 systems.

It was discovered that the AMD I3C controller has several hardware issues,
including:
- Non-functional DMA mode (defaulting to PIO mode)
- Issues with Open-Drain (OD) and Push-Pull (PP) timing parameters
- Command response buffer threshold values

All of these issues have been addressed in this series.

v1->v2:
-------
- Address LKP reported problems
- Guard boot_cpu_data usage with CONFIG_X86

Shyam Sundar S K (5):
i3c: mipi-i3c-hci: Add MIPI0100 ACPI ID to the I3C Support List
i3c: mipi-i3c-hci: Add a quirk to set PIO mode
i3c: mipi-i3c-hci: Relocate helper macros to HCI header file
i3c: mipi-i3c-hci: Add a quirk to set timing parameters
i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold

drivers/i3c/master/mipi-i3c-hci/Makefile | 3 +-
drivers/i3c/master/mipi-i3c-hci/core.c | 35 ++++++++++---
drivers/i3c/master/mipi-i3c-hci/hci.h | 12 +++++
drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 55 ++++++++++++++++++++
4 files changed, 97 insertions(+), 8 deletions(-)
create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c