Re: [PATCH 1/3] i3c: mipi-i3c-hci: Make bounce buffer code generic to all DMA transfers

[Jarkko Nikula <jarkko.nikula@linux.intel.com>]

Hi

On 6/17/25 6:09 PM, Frank Li wrote:
>> Thanks, I finially understand the problem you faced. I think other master
>> controller face similar issue if they use dma. Let me think more. If alloc
>> buffer size is not align to cache line, swtlib will bounce again.
>>
>> rough idea i3c core layer provide an i3c_(un)map_api to do that.
> 
> struct i3c_dma {
> 	void *bounce;
> 	dma_addr_t addr;
> 	enum dma_data_direction;
> 	void *data;
> 	size_t data_size;
> 	size_t bounce_size;
> }
> 
> struct i3c_dma *i3c_dma_map_single(struct device *dev, void *data, size_t sz, enum dma_data_direction dir)
> {
> 	struct i3c_dma *p
> 
> 	p = kmalloc(sizeof(*p));
> 	if (!p)
> 		return p;
> 
> 	if (is_vmalloc_addr(data)) {
> 		p->bounce = kmalloc(align_up(sz, CACHE_LINE_SIZE)); //avoid swtlib bounce again.

I'll try to look at your idea next week. Do you have pointers to the 
above allocation size rounding is it required?

I've understood from the Documentation/core-api/dma-api-howto.rst 
"Architectures must ensure that kmalloc'ed buffer is DMA-safe" and 
"ARCH_DMA_MINALIGN must be set so that the memory allocator makes sure 
that kmalloc'ed buffer doesn't share a cache line with the others.".

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