[PATCH 0/4] Add microchip sama7d65 SoC I3C support

[PATCH 0/4] Add microchip sama7d65 SoC I3C support

[Durai Manickam KR]

Add support for microchip sama7d65 SoC I3C master only IP which is based on 
mipi-i3c-hci from synopsys implementing version 1.0 specification. The platform 
specific changes are integrated in the existing mipi-i3c-hci driver by introducing 
a quirk and SoC specific config option.

I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
mixed bus mode (I2C and I3C target devices on same i3c bus).

Testing done:
With this patch we are able to fully configure the lsm6dso I3C slave
device. Unlike I2C, I hope there is no linux utility to check the
various transactions supported in the host controller. These features
will be tested later probably with I3C analyser KIT.

Durai Manickam KR (4):
  clk: at91: sama7d65: add peripheral clock for I3C
  i3c: mipi-i3c-hci: add microchip sama7d65 SoC
  ARM: configs: at91: sama7: add sama7d65 i3c-hci
  ARM: dts: microchip: add I3C controller

 arch/arm/boot/dts/microchip/sama7d65.dtsi     | 12 ++++++
 arch/arm/configs/sama7_defconfig              |  2 +
 drivers/clk/at91/sama7d65.c                   |  5 ++-
 drivers/i3c/master/mipi-i3c-hci/Makefile      |  3 +-
 drivers/i3c/master/mipi-i3c-hci/core.c        | 28 ++++++++++++
 drivers/i3c/master/mipi-i3c-hci/hci.h         | 12 ++++++
 .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++
 7 files changed, 102 insertions(+), 3 deletions(-)
 create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c

-- 
2.34.1


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[PATCH 1/4] clk: at91: sama7d65: add peripheral clock for I3C

[Durai Manickam KR]

Add peripheral clock description for I3C.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
---
 drivers/clk/at91/sama7d65.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index a5d40df8b2f2..84c6bbe20873 100644
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -671,8 +671,9 @@ static struct {
 	{ .n = "udphsa_clk",	.p = PCK_PARENT_HW_MCK5, .id = 99, },
 	{ .n = "udphsb_clk",	.p = PCK_PARENT_HW_MCK5, .id = 100, },
 	{ .n = "uhphs_clk",	.p = PCK_PARENT_HW_MCK5, .id = 101, },
-	{ .n = "dsi_clk",	.p = PCK_PARENT_HW_MCK3, .id = 103, },
-	{ .n = "lvdsc_clk",	.p = PCK_PARENT_HW_MCK3, .id = 104, },
+	{ .n = "dsi_clk",       .p = PCK_PARENT_HW_MCK3, .id = 103, },
+	{ .n = "lvdsc_clk",     .p = PCK_PARENT_HW_MCK3, .id = 104, },
+	{ .n = "i3cc_clk",      .p = PCK_PARENT_HW_MCK8, .id = 105, },
 };
 
 /*
-- 
2.34.1


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[PATCH 2/4] i3c: mipi-i3c-hci: add microchip sama7d65 SoC

[Durai Manickam KR]

Add support for microchip sama7d65 SoC I3C HCI master only IP.
Features tested and supported :
           Standard CCC commands.
           I3C SDR mode private transfers in PIO mode.
           I2C transfers in PIO mode.
           Pure bus mode and mixed bus mode.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
---
 drivers/i3c/master/mipi-i3c-hci/Makefile      |  3 +-
 drivers/i3c/master/mipi-i3c-hci/core.c        | 28 ++++++++++++
 drivers/i3c/master/mipi-i3c-hci/hci.h         | 12 ++++++
 .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++
 4 files changed, 85 insertions(+), 1 deletion(-)
 create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c

diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile
index e3d3ef757035..f463afc4566a 100644
--- a/drivers/i3c/master/mipi-i3c-hci/Makefile
+++ b/drivers/i3c/master/mipi-i3c-hci/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_MIPI_I3C_HCI)		+= mipi-i3c-hci.o
 mipi-i3c-hci-y				:= core.o ext_caps.o pio.o dma.o \
 					   cmd_v1.o cmd_v2.o \
 					   dat_v1.o dct_v1.o \
-					   hci_quirks.o
+					   hci_quirks.o \
+					   hci_quirks_mchp.o
 obj-$(CONFIG_MIPI_I3C_HCI_PCI)		+= mipi-i3c-hci-pci.o
diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 60f1175f1f37..cb0673d62c03 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -8,6 +8,7 @@
  */
 
 #include <linux/bitfield.h>
+#include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/i3c/master.h>
@@ -651,6 +652,9 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	hci->DAT_regs = offset ? hci->base_regs + offset : NULL;
 	hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval);
 	hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;
+	/* Microchip SAMA7D65 SoC doesnot support DAT entry size bits in the DAT section offset register */
+	if (hci->quirks & MCHP_HCI_QUIRK_SAMA7D65)
+		hci->DAT_entry_size = 8;
 	if (size_in_dwords)
 		hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size;
 	dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n",
@@ -661,6 +665,9 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	hci->DCT_regs = offset ? hci->base_regs + offset : NULL;
 	hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval);
 	hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16;
+	/* Microchip SAMA7D65 SoC doesnot support DCT entry size bits in the DCT section offset register */
+	if (hci->quirks & MCHP_HCI_QUIRK_SAMA7D65)
+		hci->DCT_entry_size = 16;
 	if (size_in_dwords)
 		hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size;
 	dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n",
@@ -753,6 +760,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	if (hci->quirks & HCI_QUIRK_PIO_MODE)
 		hci->RHS_regs = NULL;
 
+	/* Microchip SAMA7d65 SoC supports only PIO mode */
+	if (hci->quirks & MCHP_HCI_QUIRK_PIO_MODE)
+		hci->RHS_regs = NULL;
+
 	/* Try activating DMA operations first */
 	if (hci->RHS_regs) {
 		reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE);
@@ -788,6 +799,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
 		amd_set_od_pp_timing(hci);
 
+	/* Configure OD and PP timings for Microchip platforms */
+	if (hci->quirks & MCHP_HCI_QUIRK_OD_PP_TIMING)
+		mchp_set_od_pp_timing(hci);
+
 	return 0;
 }
 
@@ -803,6 +818,16 @@ static int i3c_hci_probe(struct platform_device *pdev)
 	if (IS_ERR(hci->base_regs))
 		return PTR_ERR(hci->base_regs);
 
+#if defined(CONFIG_SOC_SAMA7D65)
+	hci->gclk = devm_clk_get_enabled(&pdev->dev, "gclk");
+	if (IS_ERR(hci->gclk))
+		return PTR_ERR(hci->gclk);
+
+	hci->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
+	if (IS_ERR(hci->pclk))
+		return PTR_ERR(hci->pclk);
+#endif
+
 	platform_set_drvdata(pdev, hci);
 	/* temporary for dev_printk's, to be replaced in i3c_master_register */
 	hci->master.dev.init_name = dev_name(&pdev->dev);
@@ -836,6 +861,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
 
 static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
 	{ .compatible = "mipi-i3c-hci", },
+	{ .compatible = "mchp,sama7d65-i3c-hci",
+	  .data = (void *)(MCHP_HCI_QUIRK_PIO_MODE | MCHP_HCI_QUIRK_OD_PP_TIMING |
+			   MCHP_HCI_QUIRK_RESP_BUF_THLD | MCHP_HCI_QUIRK_SAMA7D65) },
 	{},
 };
 MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index 69ea1d10414b..e57f8d85402c 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -37,6 +37,10 @@ struct hci_cmd_ops;
 /* Our main structure */
 struct i3c_hci {
 	struct i3c_master_controller master;
+#if defined(CONFIG_SOC_SAMA7D65)
+	struct clk *gclk;
+	struct clk *pclk;
+#endif
 	void __iomem *base_regs;
 	void __iomem *DAT_regs;
 	void __iomem *DCT_regs;
@@ -144,6 +148,12 @@ struct i3c_hci_dev_data {
 #define HCI_QUIRK_OD_PP_TIMING		BIT(3)  /* Set OD and PP timings for AMD platforms */
 #define HCI_QUIRK_RESP_BUF_THLD		BIT(4)  /* Set resp buf thld to 0 for AMD platforms */
 
+/* list of quirks for Microchip platforms */
+#define MCHP_HCI_QUIRK_PIO_MODE		BIT(2)  /* Set PIO mode */
+#define MCHP_HCI_QUIRK_OD_PP_TIMING	BIT(3)  /* Set OD and PP timings */
+#define MCHP_HCI_QUIRK_RESP_BUF_THLD	BIT(4)  /* Set resp buf thld to 0 */
+#define MCHP_HCI_QUIRK_SAMA7D65		BIT(5)  /* Set SAMA7D65 SoC specific features */
+
 
 /* global functions */
 void mipi_i3c_hci_resume(struct i3c_hci *hci);
@@ -151,5 +161,7 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
 void amd_set_od_pp_timing(struct i3c_hci *hci);
 void amd_set_resp_buf_thld(struct i3c_hci *hci);
+void mchp_set_od_pp_timing(struct i3c_hci *hci);
+void mchp_set_resp_buf_thld(struct i3c_hci *hci);
 
 #endif
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
new file mode 100644
index 000000000000..f2e54e6643c0
--- /dev/null
+++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
+ *
+ * Authors: Durai Manickam KR <durai.manickamkr@microchip.com>
+ *
+ * Microchip I3C HCI Quirks
+ */
+
+#include <linux/i3c/master.h>
+#include "hci.h"
+
+/* Timing registers */
+#define MCHP_HCI_SCL_I3C_OD_TIMING          0x214
+#define MCHP_HCI_SCL_I3C_PP_TIMING          0x218
+#define MCHP_HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
+
+/* Timing values to configure 9MHz frequency */
+#define MCHP_SCL_I3C_OD_TIMING          0x00cf00cf
+#define MCHP_SCL_I3C_PP_TIMING          0x00160016
+
+#define MCHP_QUEUE_THLD_CTRL                0xD0
+
+void mchp_set_od_pp_timing(struct i3c_hci *hci)
+{
+	u32 data;
+
+	reg_write(MCHP_HCI_SCL_I3C_OD_TIMING, MCHP_SCL_I3C_OD_TIMING);
+	reg_write(MCHP_HCI_SCL_I3C_PP_TIMING, MCHP_SCL_I3C_PP_TIMING);
+	data = reg_read(MCHP_HCI_SDA_HOLD_SWITCH_DLY_TIMING);
+	/* Configure maximum TX hold time */
+	data |= W0_MASK(18, 16);
+	reg_write(MCHP_HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
+}
+
+void mchp_set_resp_buf_thld(struct i3c_hci *hci)
+{
+	u32 data;
+
+	data = reg_read(MCHP_QUEUE_THLD_CTRL);
+	data = data & ~W0_MASK(15, 8);
+	reg_write(MCHP_QUEUE_THLD_CTRL, data);
+}
-- 
2.34.1


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Re: [PATCH 2/4] i3c: mipi-i3c-hci: add microchip sama7d65 SoC

[Frank Li]

On Thu, Sep 18, 2025 at 03:24:27PM +0530, Durai Manickam KR wrote:
> Add support for microchip sama7d65 SoC I3C HCI master only IP.
> Features tested and supported :
>            Standard CCC commands.
>            I3C SDR mode private transfers in PIO mode.
>            I2C transfers in PIO mode.
>            Pure bus mode and mixed bus mode.
>
> Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
> ---
>  drivers/i3c/master/mipi-i3c-hci/Makefile      |  3 +-
>  drivers/i3c/master/mipi-i3c-hci/core.c        | 28 ++++++++++++
>  drivers/i3c/master/mipi-i3c-hci/hci.h         | 12 ++++++
>  .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++
>  4 files changed, 85 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile
> index e3d3ef757035..f463afc4566a 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/Makefile
> +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile
> @@ -4,5 +4,6 @@ obj-$(CONFIG_MIPI_I3C_HCI)		+= mipi-i3c-hci.o
>  mipi-i3c-hci-y				:= core.o ext_caps.o pio.o dma.o \
>  					   cmd_v1.o cmd_v2.o \
>  					   dat_v1.o dct_v1.o \
> -					   hci_quirks.o
> +					   hci_quirks.o \
> +					   hci_quirks_mchp.o
>  obj-$(CONFIG_MIPI_I3C_HCI_PCI)		+= mipi-i3c-hci-pci.o
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index 60f1175f1f37..cb0673d62c03 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -8,6 +8,7 @@
>   */
>
>  #include <linux/bitfield.h>
> +#include <linux/clk.h>
>  #include <linux/device.h>
>  #include <linux/errno.h>
>  #include <linux/i3c/master.h>
> @@ -651,6 +652,9 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	hci->DAT_regs = offset ? hci->base_regs + offset : NULL;
>  	hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval);
>  	hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;
> +	/* Microchip SAMA7D65 SoC doesnot support DAT entry size bits in the DAT section offset register */
> +	if (hci->quirks & MCHP_HCI_QUIRK_SAMA7D65)
> +		hci->DAT_entry_size = 8;

#define MCHP_HCI_QUIRK_FIX_DATA_ENTRY_SIZE_8

	if (hci->quirks & MCHP_HCI_QUIRK_FIX_DATA_ENTRY_SIZE_8)
		hci->DAT_entry_size = 8;
	else
		hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;

in case other vendor have similar problem.

>  	if (size_in_dwords)
>  		hci->DAT_entries = 4 * hci->DAT_entries / hci->DAT_entry_size;
>  	dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n",
> @@ -661,6 +665,9 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	hci->DCT_regs = offset ? hci->base_regs + offset : NULL;
>  	hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval);
>  	hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16;
> +	/* Microchip SAMA7D65 SoC doesnot support DCT entry size bits in the DCT section offset register */
> +	if (hci->quirks & MCHP_HCI_QUIRK_SAMA7D65)
> +		hci->DCT_entry_size = 16;

The same here.

>  	if (size_in_dwords)
>  		hci->DCT_entries = 4 * hci->DCT_entries / hci->DCT_entry_size;
>  	dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n",
> @@ -753,6 +760,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	if (hci->quirks & HCI_QUIRK_PIO_MODE)
>  		hci->RHS_regs = NULL;
>
> +	/* Microchip SAMA7d65 SoC supports only PIO mode */
> +	if (hci->quirks & MCHP_HCI_QUIRK_PIO_MODE)
> +		hci->RHS_regs = NULL;
> +
>  	/* Try activating DMA operations first */
>  	if (hci->RHS_regs) {
>  		reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE);
> @@ -788,6 +799,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	if (hci->quirks & HCI_QUIRK_OD_PP_TIMING)
>  		amd_set_od_pp_timing(hci);

It is worth to add a callback set_od_pp_timing() instead of use quirks.

You can create patch change existed amd one, then add mchp one.

> +	/* Configure OD and PP timings for Microchip platforms */
> +	if (hci->quirks & MCHP_HCI_QUIRK_OD_PP_TIMING)
> +		mchp_set_od_pp_timing(hci);
> +
>  	return 0;
>  }
>
> @@ -803,6 +818,16 @@ static int i3c_hci_probe(struct platform_device *pdev)
>  	if (IS_ERR(hci->base_regs))
>  		return PTR_ERR(hci->base_regs);
>
> +#if defined(CONFIG_SOC_SAMA7D65)
> +	hci->gclk = devm_clk_get_enabled(&pdev->dev, "gclk");
> +	if (IS_ERR(hci->gclk))
> +		return PTR_ERR(hci->gclk);
> +
> +	hci->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
> +	if (IS_ERR(hci->pclk))
> +		return PTR_ERR(hci->pclk);
> +#endif
> +

Use devm_clk_bulk_get_all_enabled() can be comaptible other platform.


>  	platform_set_drvdata(pdev, hci);
>  	/* temporary for dev_printk's, to be replaced in i3c_master_register */
>  	hci->master.dev.init_name = dev_name(&pdev->dev);
> @@ -836,6 +861,9 @@ static void i3c_hci_remove(struct platform_device *pdev)
>
>  static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
>  	{ .compatible = "mipi-i3c-hci", },
> +	{ .compatible = "mchp,sama7d65-i3c-hci",
> +	  .data = (void *)(MCHP_HCI_QUIRK_PIO_MODE | MCHP_HCI_QUIRK_OD_PP_TIMING |
> +			   MCHP_HCI_QUIRK_RESP_BUF_THLD | MCHP_HCI_QUIRK_SAMA7D65) },


don't suggest use cast this to pointer. You can define struct

struct mipi_csi_drvdata
{
	void (*set_op_pp_timing)();
	void **set_resp_buf_thld)();
	u32 flags;
};

static const mipi_csi_drvdata sama7d64_data = {
	.set_op_pp_timing = mchp_set_od_pp_timing;
	...
	.flags = MCHP_HCI_QUIRK_PIO_MODE;
}

.compatible = "mchp,sama7d65-i3c-hci", .data = &sama7d64_data

>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
> diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
> index 69ea1d10414b..e57f8d85402c 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/hci.h
> +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
> @@ -37,6 +37,10 @@ struct hci_cmd_ops;
>  /* Our main structure */
>  struct i3c_hci {
>  	struct i3c_master_controller master;
> +#if defined(CONFIG_SOC_SAMA7D65)
> +	struct clk *gclk;
> +	struct clk *pclk;
> +#endif

Needn't it because both are only used at probe funciton.

Frank

>  	void __iomem *base_regs;
>  	void __iomem *DAT_regs;
>  	void __iomem *DCT_regs;
> @@ -144,6 +148,12 @@ struct i3c_hci_dev_data {
>  #define HCI_QUIRK_OD_PP_TIMING		BIT(3)  /* Set OD and PP timings for AMD platforms */
>  #define HCI_QUIRK_RESP_BUF_THLD		BIT(4)  /* Set resp buf thld to 0 for AMD platforms */
>
> +/* list of quirks for Microchip platforms */
> +#define MCHP_HCI_QUIRK_PIO_MODE		BIT(2)  /* Set PIO mode */
> +#define MCHP_HCI_QUIRK_OD_PP_TIMING	BIT(3)  /* Set OD and PP timings */
> +#define MCHP_HCI_QUIRK_RESP_BUF_THLD	BIT(4)  /* Set resp buf thld to 0 */
> +#define MCHP_HCI_QUIRK_SAMA7D65		BIT(5)  /* Set SAMA7D65 SoC specific features */
> +
>
>  /* global functions */
>  void mipi_i3c_hci_resume(struct i3c_hci *hci);
> @@ -151,5 +161,7 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
>  void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
>  void amd_set_od_pp_timing(struct i3c_hci *hci);
>  void amd_set_resp_buf_thld(struct i3c_hci *hci);
> +void mchp_set_od_pp_timing(struct i3c_hci *hci);
> +void mchp_set_resp_buf_thld(struct i3c_hci *hci);
>
>  #endif
> diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
> new file mode 100644
> index 000000000000..f2e54e6643c0
> --- /dev/null
> +++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
> + *
> + * Authors: Durai Manickam KR <durai.manickamkr@microchip.com>
> + *
> + * Microchip I3C HCI Quirks
> + */
> +
> +#include <linux/i3c/master.h>
> +#include "hci.h"
> +
> +/* Timing registers */
> +#define MCHP_HCI_SCL_I3C_OD_TIMING          0x214
> +#define MCHP_HCI_SCL_I3C_PP_TIMING          0x218
> +#define MCHP_HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
> +
> +/* Timing values to configure 9MHz frequency */
> +#define MCHP_SCL_I3C_OD_TIMING          0x00cf00cf
> +#define MCHP_SCL_I3C_PP_TIMING          0x00160016
> +
> +#define MCHP_QUEUE_THLD_CTRL                0xD0
> +
> +void mchp_set_od_pp_timing(struct i3c_hci *hci)
> +{
> +	u32 data;
> +
> +	reg_write(MCHP_HCI_SCL_I3C_OD_TIMING, MCHP_SCL_I3C_OD_TIMING);
> +	reg_write(MCHP_HCI_SCL_I3C_PP_TIMING, MCHP_SCL_I3C_PP_TIMING);
> +	data = reg_read(MCHP_HCI_SDA_HOLD_SWITCH_DLY_TIMING);
> +	/* Configure maximum TX hold time */
> +	data |= W0_MASK(18, 16);
> +	reg_write(MCHP_HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
> +}
> +
> +void mchp_set_resp_buf_thld(struct i3c_hci *hci)
> +{
> +	u32 data;
> +
> +	data = reg_read(MCHP_QUEUE_THLD_CTRL);
> +	data = data & ~W0_MASK(15, 8);
> +	reg_write(MCHP_QUEUE_THLD_CTRL, data);
> +}
> --
> 2.34.1
>
>
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Re: [PATCH 2/4] i3c: mipi-i3c-hci: add microchip sama7d65 SoC

[Jarkko Nikula]

Hi

On 9/18/25 7:27 PM, Frank Li wrote:
> On Thu, Sep 18, 2025 at 03:24:27PM +0530, Durai Manickam KR wrote:
>> Add support for microchip sama7d65 SoC I3C HCI master only IP.
>> Features tested and supported :
>>             Standard CCC commands.
>>             I3C SDR mode private transfers in PIO mode.
>>             I2C transfers in PIO mode.
>>             Pure bus mode and mixed bus mode.
>>
>> Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
>> ---
>>   drivers/i3c/master/mipi-i3c-hci/Makefile      |  3 +-
>>   drivers/i3c/master/mipi-i3c-hci/core.c        | 28 ++++++++++++
>>   drivers/i3c/master/mipi-i3c-hci/hci.h         | 12 ++++++
>>   .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++
>>   4 files changed, 85 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
>>
>> diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile
>> index e3d3ef757035..f463afc4566a 100644
>> --- a/drivers/i3c/master/mipi-i3c-hci/Makefile
>> +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile
>> @@ -4,5 +4,6 @@ obj-$(CONFIG_MIPI_I3C_HCI)		+= mipi-i3c-hci.o
>>   mipi-i3c-hci-y				:= core.o ext_caps.o pio.o dma.o \
>>   					   cmd_v1.o cmd_v2.o \
>>   					   dat_v1.o dct_v1.o \
>> -					   hci_quirks.o
>> +					   hci_quirks.o \
>> +					   hci_quirks_mchp.o
>>   obj-$(CONFIG_MIPI_I3C_HCI_PCI)		+= mipi-i3c-hci-pci.o
>> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
>> index 60f1175f1f37..cb0673d62c03 100644
>> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
>> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
>> @@ -8,6 +8,7 @@
>>    */
>>
>>   #include <linux/bitfield.h>
>> +#include <linux/clk.h>
>>   #include <linux/device.h>
>>   #include <linux/errno.h>
>>   #include <linux/i3c/master.h>
>> @@ -651,6 +652,9 @@ static int i3c_hci_init(struct i3c_hci *hci)
>>   	hci->DAT_regs = offset ? hci->base_regs + offset : NULL;
>>   	hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval);
>>   	hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;
>> +	/* Microchip SAMA7D65 SoC doesnot support DAT entry size bits in the DAT section offset register */
>> +	if (hci->quirks & MCHP_HCI_QUIRK_SAMA7D65)
>> +		hci->DAT_entry_size = 8;
> 
> #define MCHP_HCI_QUIRK_FIX_DATA_ENTRY_SIZE_8
> 
> 	if (hci->quirks & MCHP_HCI_QUIRK_FIX_DATA_ENTRY_SIZE_8)
> 		hci->DAT_entry_size = 8;
> 	else
> 		hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8;
> 
> in case other vendor have similar problem.
> 
Are DAT_entry_size and DCT_entry_size quirks even needed? Does your HW 
read nonzero values and you need the quirk?

>> +	/* Microchip SAMA7d65 SoC supports only PIO mode */
>> +	if (hci->quirks & MCHP_HCI_QUIRK_PIO_MODE)
>> +		hci->RHS_regs = NULL;
>> +

Please use existing HCI_QUIRK_PIO_MODE quirk and then you don't need 
this added code.

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[PATCH 3/4] ARM: configs: at91: sama7: add sama7d65 i3c-hci

[Durai Manickam KR]

Enable the configs needed for I3C framework and microchip
sama7d65 i3c-hci driver.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
---
 arch/arm/configs/sama7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
index e14720a9a5ac..6a7455d5b7f5 100644
--- a/arch/arm/configs/sama7_defconfig
+++ b/arch/arm/configs/sama7_defconfig
@@ -115,6 +115,8 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_AT91=y
+CONFIG_I3C=y
+CONFIG_MIPI_I3C_HCI=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_ATMEL_QUADSPI=y
-- 
2.34.1


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[PATCH 4/4] ARM: dts: microchip: add I3C controller

[Durai Manickam KR]

Add I3C controller for sama7d65 SoC.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index c191acc2c89f..3a5da27f7d83 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -721,5 +721,17 @@ gic: interrupt-controller@e8c11000 {
 			#address-cells = <0>;
 			interrupt-controller;
 		};
+
+		i3c: i3c@e9000000 {
+			compatible = "mchp,sama7d65-i3c-hci";
+			reg = <0xe9000000 0x300>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>;
+			clock-names = "pclk", "gclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 105>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_ETHPLL>;
+			assigned-clock-rates = <125000000>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.34.1


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Re: [PATCH 4/4] ARM: dts: microchip: add I3C controller

[Frank Li]

On Thu, Sep 18, 2025 at 03:24:29PM +0530, Durai Manickam KR wrote:
> Add I3C controller for sama7d65 SoC.
>
> Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
> ---
>  arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index c191acc2c89f..3a5da27f7d83 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -721,5 +721,17 @@ gic: interrupt-controller@e8c11000 {
>  			#address-cells = <0>;
>  			interrupt-controller;
>  		};
> +
> +		i3c: i3c@e9000000 {
> +			compatible = "mchp,sama7d65-i3c-hci";

Need update binding doc for "mchp,sama7d65-i3c-hci"

Frank

> +			reg = <0xe9000000 0x300>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 105>, <&pmc PMC_TYPE_GCK 105>;
> +			clock-names = "pclk", "gclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 105>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_ETHPLL>;
> +			assigned-clock-rates = <125000000>;
> +			status = "disabled";
> +		};
>  	};
>  };
> --
> 2.34.1
>

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Re: [PATCH 4/4] ARM: dts: microchip: add I3C controller

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1014 bytes --]

On Thu, Sep 18, 2025 at 11:44:06AM -0400, Frank Li wrote:
> On Thu, Sep 18, 2025 at 03:24:29PM +0530, Durai Manickam KR wrote:
> > Add I3C controller for sama7d65 SoC.
> >
> > Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
> > ---
> >  arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> > index c191acc2c89f..3a5da27f7d83 100644
> > --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> > +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> > @@ -721,5 +721,17 @@ gic: interrupt-controller@e8c11000 {
> >  			#address-cells = <0>;
> >  			interrupt-controller;
> >  		};
> > +
> > +		i3c: i3c@e9000000 {
> > +			compatible = "mchp,sama7d65-i3c-hci";
> 
> Need update binding doc for "mchp,sama7d65-i3c-hci"

"mchp" isn't even a valid vendor prefix. It's not acceptable for a v2 to
be like this after the feedback on v1.

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Re: [PATCH 0/4] Add microchip sama7d65 SoC I3C support

[Rob Herring (Arm)]

On Thu, 18 Sep 2025 15:24:25 +0530, Durai Manickam KR wrote:
> Add support for microchip sama7d65 SoC I3C master only IP which is based on
> mipi-i3c-hci from synopsys implementing version 1.0 specification. The platform
> specific changes are integrated in the existing mipi-i3c-hci driver by introducing
> a quirk and SoC specific config option.
> 
> I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
> mixed bus mode (I2C and I3C target devices on same i3c bus).
> 
> Testing done:
> With this patch we are able to fully configure the lsm6dso I3C slave
> device. Unlike I2C, I hope there is no linux utility to check the
> various transactions supported in the host controller. These features
> will be tested later probably with I3C analyser KIT.
> 
> Durai Manickam KR (4):
>   clk: at91: sama7d65: add peripheral clock for I3C
>   i3c: mipi-i3c-hci: add microchip sama7d65 SoC
>   ARM: configs: at91: sama7: add sama7d65 i3c-hci
>   ARM: dts: microchip: add I3C controller
> 
>  arch/arm/boot/dts/microchip/sama7d65.dtsi     | 12 ++++++
>  arch/arm/configs/sama7_defconfig              |  2 +
>  drivers/clk/at91/sama7d65.c                   |  5 ++-
>  drivers/i3c/master/mipi-i3c-hci/Makefile      |  3 +-
>  drivers/i3c/master/mipi-i3c-hci/core.c        | 28 ++++++++++++
>  drivers/i3c/master/mipi-i3c-hci/hci.h         | 12 ++++++
>  .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++
>  7 files changed, 102 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c
> 
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/v6.17-rc1-3-g0b9dcd02ea93 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/microchip/' for 20250918095429.232710-1-durai.manickamkr@microchip.com:

arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/i3c@e9000000: failed to match any schema with compatible: ['mchp,sama7d65-i3c-hci']






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Re: [PATCH 0/4] Add microchip sama7d65 SoC I3C support

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1772 bytes --]

On Thu, Sep 18, 2025 at 03:24:25PM +0530, Durai Manickam KR wrote:
> Add support for microchip sama7d65 SoC I3C master only IP which is based on 
> mipi-i3c-hci from synopsys implementing version 1.0 specification. The platform 
> specific changes are integrated in the existing mipi-i3c-hci driver by introducing 
> a quirk and SoC specific config option.
> 
> I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
> mixed bus mode (I2C and I3C target devices on same i3c bus).
> 
> Testing done:
> With this patch we are able to fully configure the lsm6dso I3C slave
> device. Unlike I2C, I hope there is no linux utility to check the
> various transactions supported in the host controller. These features
> will be tested later probably with I3C analyser KIT.
> 
> Durai Manickam KR (4):
>   clk: at91: sama7d65: add peripheral clock for I3C
>   i3c: mipi-i3c-hci: add microchip sama7d65 SoC
>   ARM: configs: at91: sama7: add sama7d65 i3c-hci
>   ARM: dts: microchip: add I3C controller
> 
>  arch/arm/boot/dts/microchip/sama7d65.dtsi     | 12 ++++++
>  arch/arm/configs/sama7_defconfig              |  2 +
>  drivers/clk/at91/sama7d65.c                   |  5 ++-
>  drivers/i3c/master/mipi-i3c-hci/Makefile      |  3 +-
>  drivers/i3c/master/mipi-i3c-hci/core.c        | 28 ++++++++++++
>  drivers/i3c/master/mipi-i3c-hci/hci.h         | 12 ++++++
>  .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++
>  7 files changed, 102 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c

This is actually v2 right? v1 was here:
https://lore.kernel.org/all/20250910-magician-retold-a6835179f71d@spud/

Where is the dt-binding that you also omitted there?

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