Re: [PATCH RFC 4/7] i3c: add driver for Renesas I3C IP

From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Frank Li <Frank.li@nxp.com>
Cc: linux-renesas-soc@vger.kernel.org,
	Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Kees Cook <kees@kernel.org>,
	"Gustavo A. R. Silva" <gustavoars@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	linux-i3c@lists.infradead.org, linux-hardening@vger.kernel.org
Subject: Re: [PATCH RFC 4/7] i3c: add driver for Renesas I3C IP
Date: Fri, 13 Jun 2025 11:42:20 +0200	[thread overview]
Message-ID: <aEvyfM42WTKENbFO@shikoro> (raw)
In-Reply-To: <aEsDj5Vcb4zFJFlo@lizhi-Precision-Tower-5810>

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> > And there are only 8 of these registers. So, there is a maximum of 8 for
> > this controller. We could hardcode 8. But we could leave the handling as
> > is, just in case a future controller has more or less of these
> > registers.
> 
> Okay, can you point me spec link.

Overview of the SoC:
https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11ghz-cpu-and-dual-core-cortex-m33-250mhz#documents

Datasheet:
https://www.renesas.com/en/document/mah/rzg3s-group-users-manual-hardware?r=25458591

> > Sure thing. I think I didn't get feedback on my original suggestion so
> > far. If I now know you are positive about it, I will give it a try.
> 
> Sorry, linux-i3c mail list always delay your post, did you register linux-i3c
> mail list.

I did subscribe. I receive mails and my patches using git-send-email go
through directly. My responses to mails are always held back just saying
"suspicious header". But I don't know what is "suspicious", so I can't
work on it.

> > There is a specified timeout? I couldn't find one in the specs, can you
> > kindly point me to it? So, the solution is to use 100us as timeout?
> 
> See: 5.1.2.5 Controller Clock Stalling

Ah, I missed this one so far. Thanks!

> The spec have not defined what exactly happen if stall clock more than
> 100us.

I am going to the I3C Plugfest in Warszaw in 10 days. I could ask people
there...

Happy hacking,

   Wolfram

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