[PATCH v2] i3c: master: svc: Fix npcm845 FIFO_EMPTY quirk

[PATCH v2] i3c: master: svc: Fix npcm845 FIFO_EMPTY quirk

[Stanley Chu]

From: Stanley Chu <yschu@nuvoton.com>

In a private write transfer, the driver pre-fills the FIFO to work around
the FIFO_EMPTY quirk. However, if an IBIWON event occurs, the hardware
emits a NACK and the driver initiates a retry. During the retry, driver
attempts to pre-fill the FIFO again if there is remaining data, but since
the FIFO is already full, this leads to data loss.
This patch adds a condition to ensure that data is only written when there
is available space in the FIFO.

Fixes: 4008a74e0f9b ("i3c: master: svc: Fix npcm845 FIFO empty issue")
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
Changes since v1:
 remove svc_i3c_master_tx_empty helper, instead check for available FIFO space

 drivers/i3c/master/svc-i3c-master.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
index 7e1a7cb94b43..ece563353895 100644
--- a/drivers/i3c/master/svc-i3c-master.c
+++ b/drivers/i3c/master/svc-i3c-master.c
@@ -104,6 +104,7 @@
 #define   SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4)
 #define   SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0
 #define   SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x))
+#define   SVC_I3C_MDATACTRL_TXCOUNT(x) FIELD_GET(GENMASK(20, 16), (x))
 #define   SVC_I3C_MDATACTRL_TXFULL BIT(30)
 #define   SVC_I3C_MDATACTRL_RXEMPTY BIT(31)
 
@@ -1304,14 +1305,19 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master,
 		 * FIFO start filling as soon as possible after EmitStartAddr.
 		 */
 		if (svc_has_quirk(master, SVC_I3C_QUIRK_FIFO_EMPTY) && !rnw && xfer_len) {
-			u32 end = xfer_len > SVC_I3C_FIFO_SIZE ? 0 : SVC_I3C_MWDATAB_END;
-			u32 len = min_t(u32, xfer_len, SVC_I3C_FIFO_SIZE);
-
-			writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1);
-			/* Mark END bit if this is the last byte */
-			writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
-			xfer_len -= len;
-			out += len;
+			u32 space, end, len;
+
+			reg = readl(master->regs + SVC_I3C_MDATACTRL);
+			space = SVC_I3C_FIFO_SIZE - SVC_I3C_MDATACTRL_TXCOUNT(reg);
+			if (space) {
+				end = xfer_len > space ? 0 : SVC_I3C_MWDATAB_END;
+				len = min_t(u32, xfer_len, space);
+				writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1);
+				/* Mark END bit if this is the last byte */
+				writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
+				xfer_len -= len;
+				out += len;
+			}
 		}
 
 		ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
-- 
2.34.1


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Re: [PATCH v2] i3c: master: svc: Fix npcm845 FIFO_EMPTY quirk

[Frank Li]

On Mon, Jul 28, 2025 at 04:05:08PM +0800, Stanley Chu wrote:
> From: Stanley Chu <yschu@nuvoton.com>
>
> In a private write transfer, the driver pre-fills the FIFO to work around
> the FIFO_EMPTY quirk. However, if an IBIWON event occurs, the hardware
> emits a NACK and the driver initiates a retry. During the retry, driver
> attempts to pre-fill the FIFO again if there is remaining data, but since
> the FIFO is already full, this leads to data loss.

Need extra space line between two paragraphs

> This patch adds a condition to ensure that data is only written when there
> is available space in the FIFO.

submitting-patches.rst don't suggest use words "This patch"

Check available space in FIFO to prevent overflow.

Frank

>
> Fixes: 4008a74e0f9b ("i3c: master: svc: Fix npcm845 FIFO empty issue")
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> Changes since v1:
>  remove svc_i3c_master_tx_empty helper, instead check for available FIFO space
>
>  drivers/i3c/master/svc-i3c-master.c | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index 7e1a7cb94b43..ece563353895 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c
> @@ -104,6 +104,7 @@
>  #define   SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4)
>  #define   SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0
>  #define   SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x))
> +#define   SVC_I3C_MDATACTRL_TXCOUNT(x) FIELD_GET(GENMASK(20, 16), (x))
>  #define   SVC_I3C_MDATACTRL_TXFULL BIT(30)
>  #define   SVC_I3C_MDATACTRL_RXEMPTY BIT(31)
>
> @@ -1304,14 +1305,19 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master,
>  		 * FIFO start filling as soon as possible after EmitStartAddr.
>  		 */
>  		if (svc_has_quirk(master, SVC_I3C_QUIRK_FIFO_EMPTY) && !rnw && xfer_len) {
> -			u32 end = xfer_len > SVC_I3C_FIFO_SIZE ? 0 : SVC_I3C_MWDATAB_END;
> -			u32 len = min_t(u32, xfer_len, SVC_I3C_FIFO_SIZE);
> -
> -			writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1);
> -			/* Mark END bit if this is the last byte */
> -			writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
> -			xfer_len -= len;
> -			out += len;
> +			u32 space, end, len;
> +
> +			reg = readl(master->regs + SVC_I3C_MDATACTRL);
> +			space = SVC_I3C_FIFO_SIZE - SVC_I3C_MDATACTRL_TXCOUNT(reg);
> +			if (space) {
> +				end = xfer_len > space ? 0 : SVC_I3C_MWDATAB_END;
> +				len = min_t(u32, xfer_len, space);
> +				writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1);
> +				/* Mark END bit if this is the last byte */
> +				writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
> +				xfer_len -= len;
> +				out += len;
> +			}
>  		}
>
>  		ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
> --
> 2.34.1
>
>
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