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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org On Tue, Sep 01, 2026 at 07:35:31PM +0800, Billy Tsai wrote: > The DATA_TX_START_THLD field of the PIO data buffer threshold register > holds off the start of a TX transfer until the FIFO holds a set amount > of data, which in PIO mode cuts down on the number of software writes. > The field resets to 0x1, requiring at least (2 ^ 2) DWORDs (16 bytes) > in the FIFO before transmission starts. > > HCI controllers that support both PIO and DMA can expose the two as > separate register blocks; nothing in the specification says selecting > DMA mode disables the PIO block's own gating logic. On ASPEED > platforms it doesn't: DATA_TX_START_THLD still holds up transfer > start regardless of which mode feeds the FIFO, and in DMA mode that > threshold is never satisfied for some transfer sizes: > > - 1-4 bytes: uses the Immediate Data Transfer Command. > - 13+ bytes: since the hardware fetches data in 4-byte chunks, a > 13-byte transfer fetches 16 bytes into the FIFO and reaches the > threshold. > - 5-12 bytes: the threshold is never reached and the transfer stalls. > > Add HCI_QUIRK_TX_START_THLD to clear the field whenever DMA mode is > selected. The clear lives in i3c_hci_set_io_mode() rather than in > probe so the reset-and-restore recovery path also reapplies it after > a controller soft reset. Move the PIO Access Area register and > bitfield definitions from pio.c to a new pio.h so this quirk can reuse > PIO_DATA_BUFFER_THLD_CTRL and DATA_TX_START_THLD instead of > redefining them. > > Signed-off-by: Billy Tsai > Assisted-by: Claude:claude-fable-5 > --- > drivers/i3c/master/mipi-i3c-hci/core.c | 14 +++++ > drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + > drivers/i3c/master/mipi-i3c-hci/pio.c | 97 +---------------------------- > drivers/i3c/master/mipi-i3c-hci/pio.h | 109 +++++++++++++++++++++++++++++++++ > 4 files changed, 125 insertions(+), 96 deletions(-) > > diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c > index c03c3a9cbe4f..2290a889701c 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/core.c > +++ b/drivers/i3c/master/mipi-i3c-hci/core.c > @@ -26,6 +26,7 @@ > #include "cmd.h" > #include "dat.h" > #include "ibi.h" > +#include "pio.h" > > /* > * Host Controller Capabilities and Operation Registers > @@ -823,6 +824,19 @@ static int i3c_hci_set_io_mode(struct i3c_hci *hci, bool dma) > else > reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); > > + /* > + * On the ASPEED AST2700 the TX start threshold gates transfer start > + * even in DMA mode. Clear it so DMA transfers are not held back > + * waiting for a PIO FIFO level that will never be reached. > + */ > + if (dma && (hci->quirks & HCI_QUIRK_TX_START_THLD) && hci->PIO_regs) { > + void __iomem *thld_reg = hci->PIO_regs + PIO_DATA_BUFFER_THLD_CTRL; > + u32 thld_val = readl(thld_reg); > + > + thld_val &= ~DATA_TX_START_THLD; > + writel(thld_val, thld_reg); don't move these defination, original isolate is quite good. Add API or callback to implement clean DATA_TX_START_THLD. Frank -- linux-i3c mailing list linux-i3c@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-i3c