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Wed, 12 Feb 2025 19:30:05 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51CJU4w0011168 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 19:30:04 GMT Received: from [10.216.10.30] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Feb 2025 11:30:00 -0800 Message-ID: Date: Thu, 13 Feb 2025 00:59:56 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] i3c: master: Add Qualcomm I3C master controller driver To: Rob Herring CC: Krzysztof Kozlowski , , , , , , , , References: <20250205143109.2955321-1-quic_msavaliy@quicinc.com> <20250205143109.2955321-3-quic_msavaliy@quicinc.com> <1e3a103d-d468-40c6-b03c-723427d7bb41@kernel.org> <20250211214128.GB1215572-robh@kernel.org> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <20250211214128.GB1215572-robh@kernel.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YpFZhfbwHAwty72EciwSvKZwnmzTcl6W X-Proofpoint-ORIG-GUID: YpFZhfbwHAwty72EciwSvKZwnmzTcl6W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-12_06,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502120140 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_113011_253693_F822E273 X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org Thanks a lot Rob ! sorry, i was late to respond on this while waiting for other comments agreements. On 2/12/2025 3:11 AM, Rob Herring wrote: > On Mon, Feb 10, 2025 at 09:41:28PM +0530, Mukesh Kumar Savaliya wrote: >> Thanks Krzysztof ! >> >> On 2/9/2025 5:10 PM, Krzysztof Kozlowski wrote: >>> On 07/02/2025 13:03, Mukesh Kumar Savaliya wrote: >>>>>> + gi3c->se.clk = devm_clk_get(&pdev->dev, "se-clk"); >>>>>> + if (IS_ERR(gi3c->se.clk)) { >>>>>> + ret = PTR_ERR(gi3c->se.clk); >>>>>> + dev_err(&pdev->dev, "Error getting SE Core clk %d\n", ret); >>>>>> + return ret; >>>>>> + } >>>>>> + >>>>>> + ret = device_property_read_u32(&pdev->dev, "se-clock-frequency", &gi3c->clk_src_freq); >>>>> >>>>> You never tested your DTS or this code... Drop >>>>> >>>> I have tested on SM8550 MTP only. Below entry in my internal/local DTSI. >>> >>> >>> And how is it supposed to work? Are you going to send us your local >>> internal DTSI? Is it going to pass any checks? >> was saying about code was testing with MTP. DTS was tested using dt-bindings >> check. > > make dtbs_check is how you test. Sure, we are running "make dt_binding_check DT_SCHEMA_FILES=qcom,i3c-master.yaml" > >> I should add "se-clock-frequency" and "dfs-index" > > No. We already have standard clock properties and we don't put indexes > into DT. > Okay, sure Rob. I shall remove both of these and set internally within driver as they can be set to default. > Rob -- linux-i3c mailing list linux-i3c@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-i3c