From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Santosh Abraham" Date: Fri, 30 Apr 2004 11:57:27 +0000 Subject: Cache related question Message-Id: <005c01c42ea8$a22c9270$e5624c0f@india.hp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-ia64@vger.kernel.org Hi, I came to know recently that the itanium based processors do not implement the inclusion principle wrt caches ? Is this information correct ? This was a bit surprising, as I had imagined that inclusion would'nt be maitained perhaps only after a certain L1 cache size. What are the trade-offs involved ? Would there be any s/w (kernel) visible effects of not implementing inclusion ? thx, santosh.