From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Date: Sat, 04 Oct 2008 06:09:57 +0000 Subject: RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel Message-Id: <1223100597.30832.37.camel@macbook.infradead.org> List-Id: References: <20081001165750.GA21272@linux-os.sc.intel.com> <200810020951.08408.bjorn.helgaas@hp.com> <200810030941.42800.bjorn.helgaas@hp.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: "Yu, Fenghua" Cc: Bjorn Helgaas , "Luck, Tony" , Jesse Barnes , Ingo Molnar , Avi Kivity , Stephen Rothwell , Andrew Morton , LKML , "linux-ia64@vger.kernel.org" On Fri, 2008-10-03 at 17:53 -0700, Yu, Fenghua wrote: > >Architecturally, I'm surprised that ia64 would need to actually do a > >cache flush. I would think the VT-d hardware would do coherent > accesses which would make the cache flush unnecessary. > > VT-d hardware supports both non cache coherency and cache coherency by > bit Coherency in Extended Capabilities Register. But is the version without the cache coherency actually going to be _seen_ on IA64? > Could you please point me to the doc that explicitly says that > architecturally ia64 doesn't need cache flush? For safety, we can always make the driver just refuse to initialise on IA64 if the cache coherency bit isn't set. -- David Woodhouse Open Source Technology Centre David.Woodhouse@intel.com Intel Corporation