From: Keith Owens <kaos@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [PATCH] ia64: avoid broken SAL_CACHE_FLUSH implementations
Date: Mon, 30 Jan 2006 23:12:17 +0000 [thread overview]
Message-ID: <14341.1138662737@ocs3.ocs.com.au> (raw)
In-Reply-To: <200601301511.57109.bjorn.helgaas@hp.com>
Bjorn Helgaas (on Mon, 30 Jan 2006 15:11:57 -0700) wrote:
>If SAL_CACHE_FLUSH drops interrupts, complain about it and fall back to
>using PAL_CACHE_FLUSH instead.
>+ while (!ia64_get_irr(IA64_TIMER_VECTOR))
>+ ;
cpu_relax() instead of an empty loop?
Besides being the "right thing" for dual cores, it also guarantees that
the compiler will not optimize away or move the loop. ia64_get_irr()
maps to ia64_getreg() which on gcc is not optimized away, but in icc
ia64_getreg() maps to __getReg() and I am not sure if that can be
optimized or moved. The Intel compiler documentation is silent on this
topic.
FWIW, I tried the patch on SGI SN2 hardware - there was no error
message from check_sal_cache_flush().
next prev parent reply other threads:[~2006-01-30 23:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-30 22:11 [PATCH] ia64: avoid broken SAL_CACHE_FLUSH implementations Bjorn Helgaas
2006-01-30 23:12 ` Keith Owens [this message]
2006-01-30 23:32 ` Bjorn Helgaas
2006-01-30 23:58 ` Luck, Tony
2006-02-17 20:03 ` Luck, Tony
2006-02-23 16:36 ` Alex Williamson
2006-02-23 18:39 ` Luck, Tony
2006-02-23 23:11 ` Gerald Pfeifer
2006-05-01 7:20 ` Ian Wienand
2006-05-01 9:47 ` Robin Holt
2006-05-01 12:03 ` Ian Wienand
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