From: David Mosberger <davidm@napali.hpl.hp.com>
To: linux-ia64@vger.kernel.org
Subject: Re: Excessive time to handle interrupts
Date: Fri, 27 Feb 2004 00:06:07 +0000 [thread overview]
Message-ID: <16446.35311.804555.191942@napali.hpl.hp.com> (raw)
In-Reply-To: <16446.34009.722204.259663@wombat.chubb.wattle.id.au>
>>>>> On Fri, 27 Feb 2004 10:44:25 +1100, Peter Chubb <peter@chubb.wattle.id.au> said:
Peter> writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
Peter> low32 = readl(addr + IOSAPIC_WINDOW);
Peter> low32 &= ~(1 << IOSAPIC_MASK_SHIFT); /* set only the mask bit */
Peter> writel(low32, addr + IOSAPIC_WINDOW);
Peter> I don't know enough about the hardware to say for sure
See:
http://www.intel.com/design/itanium/downloads/25135001.pdf
Peter> is it feasible to keep a soft copy of the register rather
Peter> than do the read all the time? If that's not going to break
Peter> the hardware, I'll code it up and see if interrupt latencies
Peter> go down.
AFAIR, the I/O SAPIC interrupt masking is entirely under control of
the CPU (i.e., the hw never changes the mask of its own) so caching
sounds like a good idea.
FYI: I'm planning to do a q-syscollect enhancement which would let you
get at least a flat profile for code which disables interrupts (or
even interrupt collection).
--david
next prev parent reply other threads:[~2004-02-27 0:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-02-26 23:44 Excessive time to handle interrupts Peter Chubb
2004-02-27 0:06 ` David Mosberger [this message]
2004-02-27 0:18 ` Chen, Kenneth W
2004-02-27 2:07 ` Grant Grundler
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