From: David Mosberger <davidm@napali.hpl.hp.com>
To: linux-ia64@vger.kernel.org
Subject: Re: Simple Stupid Performance counters
Date: Mon, 02 May 2005 11:39:14 +0000 [thread overview]
Message-ID: <17014.4450.123162.974010@napali.hpl.hp.com> (raw)
In-Reply-To: <Pine.LNX.4.58.0504291312370.15808@schroedinger.engr.sgi.com>
>>>>> On Fri, 29 Apr 2005 13:14:33 -0700 (PDT), Christoph Lameter <clameter@engr.sgi.com> said:
Christoph> Time is measured using the cycle counter (TSC on IA32,
Christoph> ITC on IA64) which has a very low latency.
Very low latency? I guess that's relative, but at 36 cycles, AR.ITC
is one of the slowest registers. If done properly, you can normally
hide the latency of the first read (assuming you don't have too many
other AR/CR accesses pending), but I see that your macros don't do
that either:
+#define PC_START(x) x=(get_cycles() << 8) + smp_processor_id()
The shift & add ensure that even PC_START() will incur the full 36
cycle latency.
--david
next prev parent reply other threads:[~2005-05-02 11:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-04-29 20:14 Simple Stupid Performance counters Christoph Lameter
2005-04-30 1:02 ` Grant Grundler
2005-04-30 18:40 ` Christoph Lameter
2005-05-02 11:39 ` David Mosberger [this message]
2005-05-02 16:04 ` Christoph Lameter
2005-05-02 16:04 ` Grant Grundler
2005-05-02 16:08 ` Christoph Lameter
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