Re: page table lock patch V15 [0/7]: overview

Nick Piggin
2005-01-14T04:54:59Z

On Fri, 2005-01-14 at 05:39 +0100, Andi Kleen wrote:

> As you can see cmpxchg is slightly faster for the cache hot case,
> but incredibly slow for cache cold (probably because it does something
> nasty on the bus). This is pretty consistent to Intel and AMD CPUs.
> Given that page tables are likely more often cache cold than hot
> I would use the lazy variant.
>

I have a question about your trickery with the read_pte function ;)

pte_t read_pte(volatile pte_t *pte)
{
pte_t n;
do {
n.pte_low = pte->pte_low;
rmb();
n.pte_high = pte->pte_high;
rmb();
} while (n.pte_low != pte->pte_low);
return pte;
}

Versus the existing set_pte function. Presumably the order here
can't be changed otherwise you could set the present bit before
the high bit, and race with the hardware MMU?

static inline void set_pte(pte_t *ptep, pte_t pte)
{
ptep->pte_high = pte.pte_high;
smp_wmb();
ptep->pte_low = pte.pte_low;
}

Now take the following interleaving:
CPU0 read_pte CPU1 set_pte
n.pte_low = pte->pte_low;
rmb();
ptep->pte_high = pte.pte_high;
smp_wmb();
n.pte_high = pte->pte_high;
rmb();
while (n.pte_low != pte->pte_low);
return pte;
ptep->pte_low = pte.pte_low;

So I think you can get a non atomic result. Are you relying on
assumptions about the value of pte_low not causing any problems
in the page fault handler?

Or am I missing something?

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