From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@engr.sgi.com>
Date: Mon, 07 Mar 2005 23:40:56 +0000
Subject: Re: PCI Express
Message-Id: <200503071540.56781.jbarnes@engr.sgi.com>
List-Id: <linux-ia64.vger.kernel.org>
References: <4228F250.7C5E2E3C@sgi.com>
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To: linux-ia64@vger.kernel.org

On Monday, March 7, 2005 3:36 pm, Grant Grundler wrote:
> On Mon, Mar 07, 2005 at 03:11:46PM -0800, Jesse Barnes wrote:
> > So the MSIs are programmed to point at the processor SAPIC block?  I
> > think that'll work for us on Altix, but if they're pointed at an external
> > Intel (or compatible) interrupt controller, we'll have to write new code
> > for Altix.
>
> Assuming your "Processor Interrupt Block" (IIRC) is at 0xfee00000
> it should just work.

Cool, I was hoping it just pointed at the same place we use for IPIs.  It 
*should* work on Altix then, assuming the MSI allocation routines don't have 
platform knowledge in them (like ACPI bits or something).

Thanks,
Jesse