From: Bob Picco <bob.picco@hp.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [patch 0/4] ia64 SPARSEMEM
Date: Thu, 26 May 2005 21:51:09 +0000 [thread overview]
Message-ID: <20050526215109.GK23448@localhost.localdomain> (raw)
In-Reply-To: <20050523175031.GC2783@localhost.localdomain>
luck wrote: [Thu May 26 2005, 05:34:24PM EDT]
>
> >I went back and reviewed Jack's email. I must be blind but don't see why
> >he would need more than 44 bits of physical memory bits. I agree that
> >should you need 50 bits for physical address bits then you should use
> >32 bits for SECTION_SIZE_BITS.
>
> Jack's e-mail only really covered the banks of memory within a node. A
> physical address on Altix looks like this:
>
> +-------------------------------------------------------+
> | 0 | NASID | AS | BN | 00 | bank-offset |
> +-------------------------------------------------------+
>
> Where "NASID" is a physical node number ... 11 bits I think
> "AS" defines the type of memory ... 2-bits with value 0x3 for normal memory
> "BN" is the bank number within a node.
>
> A system with N nodes doesn't necessarily have NASIDs assigned 0, 1, ... N-1
>
> It is theoretically possible to build a 2-node system with NASIDs of 0 and 2047
> [though SGI have told me that this isn't usually done]. But just for grins the
> memory map for this with 4G on each of the two nodes looks like:
>
> Node 0:
> 0x0000003000000000-0x000000303FFFFFFF (bank 0)
> 0x0000003400000000-0x000000343FFFFFFF (bank 1)
> 0x0000003800000000-0x000000383FFFFFFF (bank 2)
> 0x0000003C00000000-0x0000003C3FFFFFFF (bank 3)
> Node 1:
> 0x0001FFF000000000-0x0001FFF03FFFFFFF (bank 0)
> 0x0001FFF400000000-0x0001FFF43FFFFFFF (bank 1)
> 0x0001FFF800000000-0x0001FFF83FFFFFFF (bank 2)
> 0x0001FFFC00000000-0x0001FFFC3FFFFFFF (bank 3)
>
> (and I may have slipped a binary bit here ... perhaps SGI only
> needs 49 bits, not 50).
>
okay. thanks for explanation.
> >> a smaller number ... his banks of memory all start on 4G boundaries,
> >> but could be as small as 1G ... can you have a chunk with an empty
> >> tail?).
>
> You didn't explicitly answer this question ... all the banks in the Altix
> start on 4G boundaries ... but the DIMM size is 1G ... so will this compell
> them to use a CHUNK size of 30 (to handle the 1G increment), or can they
> use 32?
Sorry. I would use 30. Unless banks need to be totally populated. For that
case 32 to reduce sectionmap size for SPARSEMEM.
>
> >Well worse case it would consume 2^(1(50-32)+3) (2 Mb). I would hope that
> >it's not configured for 28 SECTION_SIZE_BITS and 50 physical. This would
> >be excessive 2^((50-28)+3 = 32Mb and not advised.
>
> I think they need 49 and either 32 or 30 ... depending on whether a chunk
> has to be fully populated.
It doesn't have to be fully populated but we'd like to minimize reserved
pages.
>
> -Tony
bob
next prev parent reply other threads:[~2005-05-26 21:51 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-05-23 17:50 [patch 0/4] ia64 SPARSEMEM Bob Picco
2005-05-24 3:29 ` David Mosberger
2005-05-24 14:33 ` Bob Picco
2005-05-24 16:27 ` Bob Picco
2005-05-26 0:32 ` Luck, Tony
2005-05-26 20:09 ` David Mosberger
2005-05-26 20:54 ` Bob Picco
2005-05-26 21:02 ` Dave Hansen
2005-05-26 21:34 ` Luck, Tony
2005-05-26 21:44 ` Jack Steiner
2005-05-26 21:51 ` Bob Picco [this message]
2005-05-26 22:03 ` Luck, Tony
2005-05-26 22:04 ` Bob Picco
2005-05-27 5:14 ` Yasunori Goto
2005-05-27 10:35 ` Bob Picco
2005-05-27 16:23 ` David Mosberger
2005-05-27 22:04 ` Jack Steiner
2005-05-30 0:18 ` KAMEZAWA Hiroyuki
2005-05-31 17:55 ` Luck, Tony
2005-05-31 18:14 ` Dave Hansen
2005-05-31 18:15 ` Jack Steiner
2005-05-31 21:41 ` Luck, Tony
2005-05-31 21:58 ` Dave Hansen
2005-06-01 1:37 ` Bob Picco
2005-06-01 9:14 ` Andy Whitcroft
2005-06-01 22:48 ` David Mosberger
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