From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Chen, Kenneth W" Date: Fri, 31 Mar 2006 00:59:52 +0000 Subject: RE: Synchronizing Bit operations V2 Message-Id: <200603310059.k2V0x7g26953@unix-os.sc.intel.com> List-Id: In-Reply-To: References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: 'Christoph Lameter' Cc: Nick Piggin , Zoltan Menyhart , "Boehm, Hans" , "Grundler, Grant G" , akpm@osdl.org, linux-kernel@vger.kernel.org, linux-ia64@vger.kernel.org Christoph Lameter wrote on Thursday, March 30, 2006 4:51 PM > > > It precise the uncleanness in ia64 that such semantics are attached to > > > these bit operations which may lead people to depend on those. We need to > > > either make these explicit or not depend on them. > > > > I know, I'm saying since it doesn't make any difference from API point of > > view whether it is acq, rel, or no ordering, then just make them rel as a > > "preferred" Operation on ia64. > > That would make the behavior of clear_bit different from other bitops and > references to volatile pointers. I'd like to have this as consistent as > possible. Yeah, but we just agreed that caller shouldn't be thinking clear_bit has memory ordering at all. - Ken