Re: Ordering between PCI config space writes and MMIO reads?

Jeff Garzik
2006-10-24T21:37:44Z

On Tue, Oct 24, 2006 at 02:29:47PM -0700, Roland Dreier wrote:
> > It is good to be conservative in this area. Some AMD chipsets at least
> > had ordering problems with some configurations in the K7 era.
>
> Could you expand a little? Do you mean that the arch implementation
> of pci_write_config_xxx() should have extra barriers, or that drivers
> should do belt-and-suspenders flushes to make sure config writes are
> really done properly?

Drivers are -already- written to assume the pci_write_config_xxx() has
the requisite barriers. The fix doesn't belong in the drivers.

Jeff