[aegl:resctrl2_v65rc1 10/10] arch/riscv/include/asm/cacheinfo.h:17:11: error: conflicting types for 'get_cache_size'; have 'uintptr_t(u32, enum cache_type)' {aka 'long unsigned int(unsigned int, enum cache_type)'}

kernel test robot
2023-07-14T02:46:23Z

tree: https://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux.git resctrl2_v65rc1
head: b9c1779deb41e52476fa9d9d61645168d11ef092
commit: b9c1779deb41e52476fa9d9d61645168d11ef092 [10/10] resctrl2: Add the "size" file to control groups
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20230714/202307141026.5ORwMP1Y-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230714/202307141026.5ORwMP1Y-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307141026.5ORwMP1Y-lkp@intel.com/

All errors (new ones prefixed by >>):

scripts/genksyms/parse.y: warning: 9 shift/reduce conflicts [-Wconflicts-sr]
scripts/genksyms/parse.y: warning: 5 reduce/reduce conflicts [-Wconflicts-rr]
scripts/genksyms/parse.y: note: rerun with option '-Wcounterexamples' to generate conflict counterexamples
In file included from arch/riscv/include/asm/elf.h:16,
from include/linux/elf.h:6,
from include/linux/module.h:19,
from include/linux/device/driver.h:21,
from include/linux/device.h:32,
from include/linux/blk_types.h:11,
from include/linux/writeback.h:13,
from include/linux/memcontrol.h:22,
from include/linux/swap.h:9,
from include/linux/suspend.h:5,
from arch/riscv/kernel/asm-offsets.c:12:
>> arch/riscv/include/asm/cacheinfo.h:17:11: error: conflicting types for 'get_cache_size'; have 'uintptr_t(u32, enum cache_type)' {aka 'long unsigned int(unsigned int, enum cache_type)'}
17 | uintptr_t get_cache_size(u32 level, enum cache_type type);
| ^~~~~~~~~~~~~~
In file included from arch/riscv/include/asm/cacheinfo.h:9:
include/linux/cacheinfo.h:83:5: note: previous declaration of 'get_cache_size' with type 'int(int, int)'
83 | int get_cache_size(int cpu, int cache_level);
| ^~~~~~~~~~~~~~
make[3]: *** [scripts/Makefile.build:116: arch/riscv/kernel/asm-offsets.s] Error 1
make[3]: Target 'prepare' not remade because of errors.
make[2]: *** [Makefile:1275: prepare0] Error 2
make[2]: Target 'prepare' not remade because of errors.
make[1]: *** [Makefile:234: __sub-make] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:234: __sub-make] Error 2
make: Target 'prepare' not remade because of errors.

vim +17 arch/riscv/include/asm/cacheinfo.h

087958a17658dc Yash Shah 2020-02-20 15
087958a17658dc Yash Shah 2020-02-20 16 void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops);
38f5bd23deae24 Zong Li 2020-08-31 @17 uintptr_t get_cache_size(u32 level, enum cache_type type);
38f5bd23deae24 Zong Li 2020-08-31 18 uintptr_t get_cache_geometry(u32 level, enum cache_type type);
087958a17658dc Yash Shah 2020-02-20 19

:::::: The code at line 17 was first introduced by commit
:::::: 38f5bd23deae24c8fa67a2c574b6d43df27a8aa8 riscv: Add cache information in AUX vector

:::::: TO: Zong Li <zong.li@sifive.com>
:::::: CC: Palmer Dabbelt <palmerdabbelt@google.com>

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