From mboxrd@z Thu Jan  1 00:00:00 1970
From: Guy Sauvebois <Guy.Sauvebois@bull.net>
Date: Mon, 07 Jun 2004 08:23:07 +0000
Subject: bus_features in palinfo.c
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To: linux-ia64@vger.kernel.org

Hi,

If i read well, bus_features table in palinfo.c decribes
bit 52 as "Enable Cache Line Repl. Exclusive"
bit 53 as "Enable Cache Line Repl. Shared"
and Intel documentation System Architecture vol 2 (table 11-25)
defines bit 52 as "shared" and bit 53 as "exclusive".
what's right ? Intel doc I think
thanks
guy
-- 
Guy Sauvebois		tel:229 7978 ou 04 76 29 70 81
email:			Guy.Sauvebois@bull.net