Re: [PATCH] SN2 user-MMIO CPU migration

[Keith Owens <kaos@sgi.com>]

Brent Casavant (on Wed, 25 Jan 2006 11:48:57 -0600 (CST)) wrote:
>On Wed, 25 Jan 2006, Keith Owens wrote:
>
>> Brent Casavant (on Tue, 24 Jan 2006 15:12:48 -0600 (CST)) wrote:
>> >+void sn_switch_from(struct task_struct *task)
>> >+{
>> >+	pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
>> >+	volatile unsigned long *adr = last_pda->pio_write_status_addr;
>> >+	unsigned long val = last_pda->pio_write_status_val;
>> >+
>> >+	/* Drain PIO writes from old CPU's Shub */
>> >+	while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
>> >+		cpu_relax();
>> >+}
>> 
>> cpu_relax() maps to ia64_hint(ia64_hint_pause) which is defined as a
>> memory clobber, so you do not need to mark adr as volatile.  Linus
>> recommends against relying on volatile in C code, memory barrier
>> operations like cpu_relax should be used instead.
>
>Hmm.  Does that mean that the SN mmiowb() implementation is incorrect
>as well?  Because this was pretty much a cut-n-paste job from there.

Yes.

>I can probably fix that (mmiowb()) in the near future, as there's
>some upcoming work needed in that area.
>
>> Alas include/asm-ia64/intel_intrin.h defines ia64_hint() as a no-op.
>
>Err, so we should hold off on fixing this plus mmiowb() until the
>intrinsic is fixed, correct?

Yes.