From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Owens Date: Tue, 31 Jan 2006 08:57:12 +0000 Subject: Re: [patch 1/6] align kenrel rbs on 128 byte Message-Id: <6389.1138697832@kao2.melbourne.sgi.com> List-Id: References: <200601310848.k0V8mbg11087@unix-os.sc.intel.com> In-Reply-To: <200601310848.k0V8mbg11087@unix-os.sc.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-ia64@vger.kernel.org "Chen, Kenneth W" (on Tue, 31 Jan 2006 00:48:28 -0800) wrote: >The bottom of kernel rbs stack is the memory used to spill user >dirty stack register partition when entering the kernel. This >space is heavily used on every kernel entry and exit. It deserve >having its own dedicated cache line and not to share with tail >end of thread_info which is not used heavily. > >Align the bottom of kernel rbs stack to 128 byte boundary. > >Signed-off-by: Ken Chen > > >--- ./include/asm-ia64/ptrace.h.orig 2006-01-19 16:45:49.695591377 -0800 >+++ ./include/asm-ia64/ptrace.h 2006-01-20 02:24:05.985205410 -0800 >@@ -75,7 +75,7 @@ > # define KERNEL_STACK_SIZE_ORDER 0 > #endif > >-#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 15) & ~15) >+#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 127) & ~127) > #define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE) > > #define KERNEL_STACK_SIZE IA64_STK_OFFSET The cache lines are not guaranteed to be 128 byte aligned, they were 64 on bigsur. Change 127 to (L1_CACHE_BYTES - 1).