From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christian Hildner Date: Thu, 28 Feb 2002 08:06:54 +0000 Subject: Re: [Linux-ia64] VHPT performance Message-Id: List-Id: References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-ia64@vger.kernel.org David Could you please send me your test program to verify this. Since I haven't fixed the storage in my test prog maybe there are additional page faults. Is it possible to fix malloc() storage from userspace? Thanks Christian David Mosberger schrieb: > >>>>> On Fri, 22 Feb 2002 12:35:51 +0100, Christian Hildner said: > > Christian> I made some measures and found that on Itanium it takes > Christian> about ~700 CPU cycles to load a single byte when TLB is > Christian> missing and VHPT is enabled vs. ~900 cycles with VHPT > Christian> disabled and handling the TLB miss in the IVT. > > It's not that simple. On Itanium, the VHPT will help only if the TLB > entry can be found in the cache (this is described in the Itanium > microarch. manual, IIRC). I don't think anything has been said > publically yet what McKinley does, so we'll have to wait a bit longer. > > The 700 cycle number sounds too high. For example, I have a little > test program that shows repeatedly touching ~92 pages takes about 25 > cycles on average and touching more than 128 pages takes about 73 > cycles on average, for a difference of about 48 cycles. > > Christian> Does > Christian> anybody know if the VHPT walker is implemented in > Christian> hardware (probably not), microcode (that's what I think) > Christian> or unimplemented at all? > > It's definitely implemented in hardware, though I don't know the > implementation details. > > --david