Matt,

On Fri, May 10, 2002 at 07:20:06PM +1000, Matt Chapman wrote:
> * Linux 2.4.18-ia64-020508 (CONFIG_PERFMON, !CONFIG_DISABLE_VHPT)
> * pfmon 1.0
> * Uniprocessor Itanium C1-step 
> * lat_ctx from LMbench 2.0p2 (ftp://ftp.bitmover.com/lmbench/)
> 
> (Though I get the same results with 2.4.16 and pfmon 0.06a.)
> 
> % pfmon -e ITLB_MISSES_FETCH,ITLB_INSERTS_HPW ./lat_ctx 5
> 
> "size=0k ovr=2.65
> 5 2.52
>                221400 ITLB_MISSES_FETCH
>                   133 ITLB_INSERTS_HPW
> 
> The ITLB misses figure seems much too big, especially given the number
> of hardware pagetable walker inserts is low.  Every few times I also get
> very big figures for DTLB_MISSES, although not DTC_MISSES (I would have
> thought DTLB_MISSES should be less than DTC_MISSES?).
> 
> Am I doing something wrong?
> 

I was able to reproduce what you are seing. In fact, I tried measuring
the same event using a different program. The LMbench test involves
several processes competing for the CPU. I used a single process instead.
I verified with the knowlegeable people that the counter is not bogus. 
However it does count more than what you'd expect. It counts all the 
detected ITLB misses (including a demand fetch), however not all of them 
end up in a translation being inserted because they get cancelled. This can 
happen because of prefetching and branch prediction. So if a branch is 
mispredicted, the ITLB misses generated by the (wrong) prediction will get 
cancelled but they are counted.

The attached test program stresses the TLB by having one function
per page. It involves an indirect branch which (most likely) is always
mispredicted. Now if you increase the number of iteration with a constant
(and small) number of functions called, you see the ITLB_MISSES_FETCH count
increase linearly. If you modify the assembly code and try to avoid
the misprediction with a hinted mov to br (mov.sptk.imp), then you suddenly
see the ITLB_MISSES_FETCH remain constant.

Hope this helps.

-- 
-Stephane